s-24c128ci-t8t1u3 Seiko Instruments Inc., s-24c128ci-t8t1u3 Datasheet - Page 17

• Manufacturer Part Number: s-24c128ci-t8t1u3
• Description: 2-wire Serial Eeprom S-24c128c 128k-bit
• Manufacturer: Seiko Instruments Inc.

LINE
SDA
Rev.2.0
S
A
R
T
T
7. 2 Random Read
M
S
B
1 0 1 0
Random read is used to read the data at an arbitrary memory address.
A dummy write is performed to load the memory address into the address counter.
When the S-24C128C receives a 7-bit device address and a 1-bit read / write instruction code set to “0”
following a start condition, it responds with an acknowledge.
The S-24C128C then receives a upper 8-bit word address and responds with an acknowledge. And the S-
24C128C receives a lower 8-bit word address and responds with an acknowledge. The memory address is
loaded to the address counter in the S-24C128C by these operations. Reception of write data does not follow
in a dummy write whereas reception of write data follows in byte write and in page write.
Since the memory address is loaded into the memory address counter by dummy write, the master device can
read the data starting from the arbitrary memory address by transmitting a new start condition and performing
the same operation in the current address read.
That is, when the S-24C128C receives a 7-bit device address and a 1-bit read / write instruction code set to
“1”, following a start condition signal, it responds with an acknowledge. Next, 8-bit data is transmitted from the
S-24C128C in synchronous to the SCL clock. The master device outputs stop condition not an acknowledge,
the reading of S-24C128C is ended.
_00_H
ADDRESS
DEVICE
A2 A1 A0
S
B
L
W
W
R
R
E
T
0
/
I
C
A
K
X
X
DUMMY WRITE
WORD ADDRESS
X W13
UPPER
W12 W11 W10
W9W8
Figure 17 Random Read
Seiko Instruments Inc.
A
C
K
W7 W6 W5 W4 W3 W2 W1
WORD ADDRESS
LOWER
W0
A
C
K
2-WIRE CMOS SERIAL E
S
T
A
R
T
M
S
B
1 0 1 0
ADDRESS
DEVICE
A2 A1 A0
S
B
L
W
R
R
E
A
D
1
/
C
A
K
D7 D6 D5 D4 D3 D2 D1 D0
下図へ続く
S-24C128C
NO ACK from
Master Device
DATA
2
PROM
17
O
S
T
P