s-24c128ci-t8t1u3 Seiko Instruments Inc., s-24c128ci-t8t1u3 Datasheet - Page 26

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s-24c128ci-t8t1u3

Manufacturer Part Number
s-24c128ci-t8t1u3
Description
2-wire Serial Eeprom S-24c128c 128k-bit
Manufacturer
Seiko Instruments Inc.
Datasheet
26
2-WIRE CMOS SERIAL E
S-24C128C
6. Data hold time (t
7. SDA pin and SCL pin noise suppression time
If SCL and SDA of the S-24C128C are changed at the same time, it is necessary to prevent a start / stop condition
from being mistakenly recognized due to the effect of noise.
The S-24C128C may error if it does not recognize a start / stop condition correctly during transmission.
It is recommended to set the delay time of 0.3 s minimum from a falling edge of SCL for the SDA.
This is to prevent S-24C128C from going in a start / stop condition due to the time lag caused by the load of the
bus line.
The S-24C128C includes a built-in low-pass filter at the SDA and SCL pins to suppress noise. This means that if
the power supply voltage is 5.0 V, noise with a pulse width of 130 ns or less can be suppressed.
For details of the assurable value, refer to noise suppression time (t
Noise Suppression Time (t
SDA
SCL
HD.DAT
Figure 29 Noise Suppression Time for SDA and SCL Pins
[ns]
= 0 ns)
2
PROM
Figure 28 S-24C128C Data Hold Time
I
) Max.
Seiko Instruments Inc.
t
HD.DAT
300
200
100
= 0.3 s Min.
Power supply voltage (V
2
l
) in Table 12.
[V]
3
4
CC
)
5
Rev.2.0
_00_H

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