m58wr032et STMicroelectronics, m58wr032et Datasheet - Page 7

• Manufacturer Part Number: m58wr032et
• Description: 32 Mbit 2mb X 16, Multiple Bank, Burst 1.8v Supply Flash Memory
• Manufacturer: STMicroelectronics

SUMMARY DESCRIPTION
The M58WR032E is a 32 Mbit (2Mbit x16) non-vol-
atile Flash memory that may be erased electrically
at block level and programmed in-system on a
Word-by-Word basis using a 1.65V to 2.2V V
supply for the circuitry and a 1.65V to 3.3V V
supply for the Input/Output pins. An optional 12V
V
er programming.
The device features an asymmetrical block archi-
tecture. M58WR032E has an array of 71 blocks,
and is divided into 4 Mbit banks. There are 7 banks
each containing 8 main blocks of 32 KWords, and
one parameter bank containing 8 parameter
blocks of 4 KWords and 7 main blocks of 32
KWords. The Multiple Bank Architecture allows
Dual Operations, while programming or erasing in
one bank, Read operations are possible in other
banks. Only one bank at a time is allowed to be in
Program or Erase mode. It is possible to perform
burst reads that cross bank boundaries. The bank
architecture is summarized in
memory maps are shown in
eter Blocks are located at the top of the memory
address space for the M58WR032ET, and at the
bottom for the M58WR032EB.
Each block can be erased separately. Erase can
be suspended, in order to perform program in any
other block, and then resumed. Program can be
suspended to read data in any other block and
then resumed. Each block can be programmed
and erased over 100,000 cycles using the supply
voltage V
programming commands available to speed up
programming.
Program and Erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
PP
power supply is provided to speed up custom-
DD
. There are two Enhanced Factory
Figure 4.
Table
The Param-
2., and the
DDQ
DD
control the memory is consistent with JEDEC stan-
dards.
The device supports synchronous burst read and
asynchronous read from all blocks of the memory
array; at power-up the device is configured for
asynchronous read. In synchronous burst mode,
data is output on each clock cycle at frequencies
of up to 54MHz.
The device features an Automatic Standby mode.
When the bus is inactive during asynchronous
read operations, the device automatically switches
to the Automatic Standby mode. In this condition
the power consumption is reduced to the standby
value I
The M58WR032E features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When V
program or erase. All blocks are locked at Power-
Up.
The device includes a Protection Register and a
Security Block to increase the protection of a sys-
tem’s design. The Protection Register is divided
into two segments: a 64 bit segment containing a
unique device number written by ST, and a 128 bit
segment One-Time-Programmable (OTP) by the
user. The user programmable segment can be
permanently protected. The Security Block, pa-
rameter block 0, can be permanently protected by
the user.
Protection Register Memory Map.
The memory is offered in a VFBGA56, 7.7 x 9 mm
0.75 mm ball pitch package and is supplied with all
the bits erased (set to ’1’).
DD4
PP
Figure
and the outputs are still driven.
V
PPLK
M58WR032ET, M58WR032EB
5., shows the Security Block and
all blocks are protected against
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