e28f016xd Intel Corporation, e28f016xd Datasheet - Page 6

• Manufacturer Part Number: e28f016xd
• Description: 16-mbit 1 Mbit X 16 Dram-interface Flash Memory
• Manufacturer: Intel Corporation

28F016XD FLASH MEMORY
block. In addition, the 28F016XD has a master
Write Protect pin (WP#) which prevents any
modifications to memory blocks whose lock-bits
are set.
Writing of memory data is performed in word
increments typically within 6 µs (12.0V V
33% improvement over the 28F008SA. A block
erase operation erases one of the 32 blocks in
typically 0.6 sec (12.0V V
other blocks, which is about a 65% improvement
over the 28F008SA.
Each block can be written and erased a minimum
of 100,000 cycles. Systems can achieve one
million Block Erase Cycles by providing wear-
leveling algorithms and graceful block retirement.
These techniques have already been employed in
many flash file systems and hard disk drive
designs.
All operations are started by a sequence of Write
commands to the device. Three types of Status
Registers (described in detail later in this
datasheet) and a RY/BY# output pin provide
information on the progress of the requested
operation.
The following Status Registers are used to provide
device and WSM information to the user :
The GSR and BSR memory maps are shown in
Figure 4.
6
A Compatible Status Register (CSR) which is
100% compatible with the 28F008SA FlashFile
memory Status Register. The CSR, when used
alone, provides a straightforward upgrade
capability to the 28F016XD from a 28F008SA-
based design.
A Global Status Register (GSR) which also
informs the system of overall Write State
Machine (WSM) status.
32 Block Status Registers (BSRs) which
provide block-specific status information such
as the block lock-bit status.
PP
), independent of the
PP
)—a
The 28F016XD incorporates an open drain
RY/BY# output pin. This feature allows the user to
OR-tie many RY/BY# pins together in a multiple
memory configuration such as a Resident Flash
Array.
The 28F016XD is specified for a maximum fast
page mode cycle time of 65 ns (t
operation (4.75V to 5.25V) over the commercial
temperature
corresponding maximum fast page mode cycle
time of 75 ns at 3.3V (3.0V to 3.6V and 0 C to
+70 C)
consumption applications.
The 28F016XD incorporates an Automatic Power
Saving (APS) feature, which substantially reduces
the active current when the device is in static
mode of operation (addresses not switching). In
APS mode, the typical I
(3.0 mA at 3.3V).
A deep power-down mode of operation is invoked
when the RP# (called PWD# on the 28F008SA)
pin transitions low. This mode brings the device
power consumption to less than 2.0 µA, typically,
and provides additional write protection by acting
as a device reset pin during power transitions. A
reset time of 300 ns (5.0V V
required from RP# switching high until dropping
RAS#. In the deep power-down state, the WSM is
reset (any current operation will abort) and the
CSR, GSR and BSR registers are cleared.
A CMOS standby mode of operation is enabled
when RAS# and CAS# transition high and RP#
stays high with all input control pins at CMOS
levels. In this mode, the device typically draws an
I
The 28F016XD is available in a 56-Lead, 1.2 mm
thick, 14 mm x 20 mm TSOP Type I package. This
form factor and pinout allow for very high board
layout densities.
2.0 DEVICE PINOUT
The 28F016XD 56-Lead TSOP Type I pinout
configuration is shown in Figure 2.
CC
standby current of 70 µA at 5.0V V
is
achieved
range
CC
(0 C
current is 1 mA at 5.0V
for
CC
to
reduced
E
operation)
PC,R
+70 C).
CC
.
) at 5.0V
power
is
A