nsbmc290 National Semiconductor Corporation, nsbmc290 Datasheet - Page 15

• Manufacturer Part Number: nsbmc290
• Description: Burst Mode Memory Controller
• Manufacturer: National Semiconductor Corporation

5A t
6A t
8A t
10 t
11 t
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
22 t
23 t
24 t
25 t
26 t
27 t
28 t
29 t
30 t
31 t
32 t
33 t
34 t
9 t
1 t
2 t
3 t
4 t
5 t
6 t
7 t
8 t
AC Timing Parameters
Note 1 Derate the given delays by 0 06 ns per pF of load in excess of 50 pF
Note 2 Where t
Signal output delays are measured relative to SYSCLK (except as indicated) using a 50 pF load
Symbol
BSU
BH
RQSU
RQH
SU
SU
H
BRH
ARA
RAH
DRAH
CAV
CAH
RSHL
RSLH
CHL
CLH
PZH
PHL
PLH
PHZ
RZH
RHL
RLH
RHZ
LEHL
LELH
BHL
BLH
RWSU
RWH
WEV
BKZH
BKHL
BKLH
BKHZ
ABKLH
BlNV Setup
BINV Hold
Request Sync Setup Time
Request Sync Hold Time
Synchronous Input Setup
Synchronous Input Setup I DBREQ only
Synchronous Input Hold
Address Input to Row Address output delay
(Note 1)
DRAM Row Address Hold (Note 2)
(Note 1)
SYSCLK to Column Address Hold
SYSCLK to RAS Asserted Delay (Note 1)
SYSCLK to RAS De-asserted Delay (Note 1)
SYSCLK to CAS Asserted Delay (Note 1)
SYSCLK to CAS De-asserted (Note 1)
PEN 3-state to Valid Delay Relative to
PEN Synchronous Assertion Delay
PEN Synchronous Deassertion Delay
PEN Valid to 3-state Delay Relative to
RDY 3-state to Valid Delay Relative to
RDY Synchronous Assertion Delay
RDY Synchronous De-assertion Delay
RDY Valid to 3-state Delay Relative to
Synchronous Latch Enable Assertion delay
Synchronous Latch Enable De-assertion Delay
Synchronous Buffer Enable Assertion Delay
Synchronous Buffer Enable De-assertion Delay
Synchronous R W Input Setup Time
Synchronous R W Input Hold Time
Synchronous Write Enable Valid Delay
Relative to SYSCLK
Synchronous I DBACK Valid Delay
Synchronous I DBACK Assertion Delay
Synchronous I DBACK Deassertion Delay
Synchronous I DBACK Valid to 3-state Delay
Asynchronous I DBACK Deassertion delay
relative to I DREQ
CLK
SYSCLK to Burst Request Input Hold
SYSCLK to row address hold
SYSCLK to Column Address Valid Delay
SYSCLK
SYSCLK
SYSCLK
SYSCLK
e
1 (2
Clock Frequency)
Description
(Unless otherwise stated V
15
t
CC
CLK
Min
17
17
16 MHz
8
4
4
9
4
4
9
6
8
4
e
-4
5 0V
Max
29
38
26
23
32
40
30
26
25
29
30
26
25
29
32
42
49
38
59
25
29
24
24
22
g
5% 0 C
t
CLK
Min
13
13
20 MHz
7
3
3
8
3
3
8
6
7
3
-4
k
Max
24
32
22
19
27
33
25
22
21
24
25
22
21
24
27
35
41
32
49
21
24
20
20
18
T
A k
t
CLK
Min
70 C )
12
12
25 MHz
6
3
3
6
3
3
7
5
6
3
-3
Max
22
29
20
17
24
30
23
20
19
22
23
20
19
22
24
32
37
29
44
19
22
18
18
14
t
CLK
Min
4 5
10
10
33 MHz
5
2
2
2
2
6
5
5
2
-2
Max
18
24
17
14
20
25
19
17
16
18
19
17
16
18
20
26
31
24
37
16
18
15
15
12
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns