nsbmc290 National Semiconductor Corporation, nsbmc290 Datasheet - Page 16

• Manufacturer Part Number: nsbmc290
• Description: Burst Mode Memory Controller
• Manufacturer: National Semiconductor Corporation

1
2
3
4
5
6
7
8
AC Timing Parameters
Note Buffer control signal timing is illustrated using the mode dependent signal naming convention (See page 7 ) As shown the switching behavior is typical of
modes 0 and 1 In modes 2 and 3 the timing of signals DBTX DBCE and IBTX remain unchanged
Note 1 Derate given the delays by 0 06 ns per pF or load in excess of 50 pF
TXa
Signal output delays are measured relative to SYSCLK (except as indicated) using a 50 pF load
Symbol
t
t
t
t
t
t
t
t
CHL
CLH
CAV
CAH
BHL
BLH
LEHL
LELH
e
IBTXa DBTXa CEa
SYSCLK to CAS De-Assertion (Note 1)
SYSCLK to Buffer Control Assertion Delay
SYSCLK to Latch Enable De-Assertion
SYSCLK to CAS Assertion (Note 1)
SYSCLK to Column Address Valid Delay (Note 1)
SYSCLK to Column Address Hold Time (Note 1)
SYSCLK to Buffer Control De-Assertion Delay
SYSCLK to Latch Enable Assertion
e
IBCEa DBCE TXb
Description
(Continued)
TABLE VIII Burst Access Timing Parameters
e
IBTXb DBTXb CEb
FIGURE 6 Burst Access Timing
e
16
IBCEb DBCEb and BANKb a
Min
6
16 MHz
Max
25
24
38
34
25
24
26
26
Min
5
20 MHz
Max
21
20
32
28
21
20
22
22
Min
5
25 MHz
Max
19
18
29
25
19
18
20
20
Min
3
33 MHz
Max
15 5
15 5
16 5
16 5
TL V 11803 – 7
15
24
21
15
Units
ns
ns
ns
ns
ns
ns
ns
ns