lm5025asdx National Semiconductor Corporation, lm5025asdx Datasheet - Page 12

• Manufacturer Part Number: lm5025asdx
• Description: Active Clamp Voltage Mode Pwm Controller
• Manufacturer: National Semiconductor Corporation

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Current Limit
the PWM comparator will produce the first output pulse at
OUT_A. After the first pulse occurs, the softstart current
source will revert to the normal 20µA level. Fully discharging
and then slowly charging the SS capacitor protects a con-
tinuously over-loaded converter with a low duty cycle hiccup
mode.
These two modes of over-current protection allow the user
great flexibility to configure the system behavior in over-load
conditions. If it is desired for the system to act as a current
source during an over-load, then the CS1 cycle-by-cycle
current limiting should be used. In this case the current
sense signal should be applied to the CS1 input and the CS2
input should be grounded. If during an overload condition it is
desired for the system to briefly shutdown, followed by soft-
start retry, then the CS2 hiccup current limiting mode should
be used. In this case the current sense signal should be
applied to the CS2 input and the CS1 input should be
grounded. This shutdown / soft-start retry will repeat indefi-
nitely while the over-load condition remains. The hiccup
mode will greatly reduce the thermal stresses to the system
during heavy overloads. The cycle-by-cycle mode will have
higher system thermal dissipations during heavy overloads,
but provides the advantage of continuous operation for short
duration overload conditions.
It is possible to utilize both over-current modes concurrently,
whereby slight overload conditions activate the CS1 cycle-
by-cycle mode while more severe overloading activates the
CS2 hiccup mode. Generally the CS1 input will always be
configured to monitor the main switch FET current each
cycle. The CS2 input can be configured in several different
ways depending upon the system requirements.
a) The CS2 input can also be set to monitor the main switch
FET current except scaled to a higher threshold than CS1
Oscillator and Sync Capability
The LM5025A oscillator is set by a single external resistor
connected between the RT pin and GND. To set a desired
oscillator frequency (F), the necessary RT resistor can be
calculated from:
where F is in kHz and RT in kΩ.
The RT resistor should be located very close to the device
and connected directly to the pins of the IC (RT and GND).
A unique feature of LM5025A is the ability to synchronize the
oscillator to an external clock with a frequency that is either
higher or lower than the frequency of the internal oscillator.
The lower frequency sync frequency range is 80% of the free
running internal oscillator frequency. There is no constraint
on the maximum SYNC frequency. A minimum pulse width of
100ns is required for the synchronization clock . If the syn-
RT = (5725/F)
(Continued)
1.026
12
b) An external over-current timer can be configured which
trips after a pre-determined over-current time, driving the
CS2 input high, initiating a hiccup event.
c) In a closed loop voltage regulaton system, the COMP
input will rise to saturation when the cycle-by-cycle current
limit is active. An external filter/delay timer and voltage di-
vider can be configured between the COMP pin and the CS2
pin to scale and delay the COMP voltage. If the CS2 pin
voltage reaches 0.5V a hiccup event will initiate.
A small RC filter, located near the controller, is recom-
mended for each of the CS pins. The CS1 input has an
internal FET which discharges the current sense filter ca-
pacitor at the conclusion of every cycle, to improve dynamic
performance. This same FET remains on an additional 50ns
at the start of each main switch cycle to attenuate the leading
edge spike in the current sense signal. The CS2 discharge
FET only operates following a CS2 event, UVLO and thermal
shutdown.
The LM5025A CS comparators are very fast and may re-
spond to short duration noise pulses. Layout considerations
are critical for the current sense filter and sense resistor. The
capacitor associated with the CS filter must be placed very
close to the device and connected directly to the pins of the
IC (CS and GND). If a current sense transformer is used,
both leads of the transformer secondary should be routed to
the filter network , which should be located close to the IC. If
a sense resistor in the source of the main switch MOSFET is
used for current sensing, a low inductance type of resistor is
required. When designing with a current sense resistor, all of
the noise sensitive low power ground connections should be
connected together near the IC GND and a single connec-
tion should be made to the power ground (sense resistor
ground point).
chronization feature is not required, the SYNC pin should be
connected to GND to prevent any abnormal interference .
The internal oscillator can be completely disabled by con-
necting the RT pin to REF. Once disabled, the sync signal
will act directly as the master clock for the controller. Both the
frequency and the maximum duty cycle of the PWM control-
ler can be controlled by the SYNC signal (within the limita-
tions of the Volt x Second Clamp). The maximum duty cycle
(D) will be (1-D) of the SYNC signal.
Feed-Forward Ramp
An external resistor (R
V
The slope of the signal at the RAMP pin will vary in propor-
tion to the input line voltage. This varying slope provides line
feedforward information necessary to improve line transient
response with voltage mode control. The RAMP signal is
IN
and GND are required to create the PWM ramp signal.
FF
) and capacitor (C
FF
20107414
) connected to