lm5025asdx National Semiconductor Corporation, lm5025asdx Datasheet - Page 3

• Manufacturer Part Number: lm5025asdx
• Description: Active Clamp Voltage Mode Pwm Controller
• Manufacturer: National Semiconductor Corporation

Pin Description
PIN
10
11
12
13
14
15
16
8
9
-
OUT_A
OUT_B
NAME
COMP
PGND
AGND
SYNC
UVLO
SS
RT
EP
Main output driver
Active Clamp output driver
Power ground
Analog ground
Soft-start control
Input to the Pulse Width Modulator
Oscillator timing resistor pin
Oscillator UP/DOWN synchronization input
Line Under-Voltage shutdown
Exposed PAD, underside of the LLP package
option
(Continued)
DESCRIPTION
3
Output of the main switch PWM output gate driver.
Output capability of 3A peak sink current.
Output of the Active Clamp switch gate driver.
Capable of 1.25A peak sink current..
Connect directly to analog ground.
Connect directly to power ground. For the LLP
package option the exposed pad is electrically
connected to AGND.
An external capacitor and an internal 20µA current
source set the softstart ramp. The SS current source
is reduced to 1uA initially following a CS2
over-current event or an over temperature event.
An internal 5KΩ resistor pull-up is provided on this
pin. The external opto-coupler sinks current from
COMP to control the PWM duty cycle.
An external resistor connected from RT to ground
sets the internal oscillator frequency.
The internal oscillator can be synchronized to an
external clock with a frequency 20% lower than the
internal oscillator’s free running frequency. There is
no constraint on the maximum sync frequency.
An external voltage divider from the power source
sets the shutdown comparator levels. The
comparator threshold is 2.5V. Hysteresis is set by an
internal current source (20µA) that is switched on or
off as the UVLO pin potential crosses the 2.5V
threshold.
Internally bonded to the die substrate. Connect to
GND potential for low thermal impedance.
APPLICATION INFORMATION
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