tza3012hw NXP Semiconductors, tza3012hw Datasheet - Page 11

• Manufacturer Part Number: tza3012hw
• Description: Tza3012hw 30 Mbits/s Up To 3.2 Gbits/s A-rate Fiber-optic Receiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 8:
V
voltages are referenced to ground; positive currents flow into the device; unless otherwise specified.
[1]
[2]
[3]
Table 9:
V
voltages are referenced to ground; positive currents flow into the device; unless otherwise specified.
Table 10:
V
voltages are referenced to ground; positive currents flow into the device; unless otherwise specified.
TZA3012HW_1
Product data sheet
Symbol
CMOS output: pins LOS1 and LOS2
V
V
Symbol
Reference input frequency: pins CREF and CREFQ
V
V
Z
f
PLL characteristics
t
t
t
TDR
Symbol
Serial input: pins CLOOP, CLOOPQ, DLOOP and DLOOPQ
V
V
Z
t
t
t
i(ref)
acq
acq(pc)
acq(oc)
d
su
h
CC
CC
CC
clk
i
f
i
OL
OH
i(p-p)
I
i(p-p)
I
i(ref)
= 3.14 V to 3.47 V; T
The RF input is protected against a differential overvoltage; the maximum input current is 30 mA. It is assumed that both inputs carry a
complementary signal of the specified peak-to-peak value.
The slice level is adjustable in 256 steps controlled by I
The hysteresis is adjustable in 8 steps controlled by bits HYS1 and HYS2 in I
LIMLOS2CNF (address BFh).
= 3.14 V to 3.47 V; T
= 3.14 V to 3.47 V; T
max
Parameter
LOW-state output voltage
HIGH-state output voltage
Parameter
peak-to-peak input voltage
input voltage
input impedance
reference input frequency
reference input frequency accuracy
acquisition time
power cycle acquisition time
octave change acquisition time
maximum transitionless data run
Parameter
peak-to-peak input voltage
input voltage
input impedance
delay time
setup time
hold time
clock duty cycle
RF input, RSSI and LOS characteristics
Clock and PLL characteristics
Serial input and output characteristics
amb
amb
amb
= 40 C to 85 C; R
= 40 C to 85 C; R
= 40 C to 85 C; R
Rev. 01 — 15 December 2005
Conditions
single-ended
single-ended to V
data DLOOP and DLOOPQ to
clock CLOOP and CLOOPQ;
between differential crossovers
referenced to negative clock edge
see
see
clock CLOOP and CLOOPQ;
between differential crossovers
Conditions
I
I
Conditions
single-ended
single-ended to V
R = 1, 2, 4 or 8
SDH/SONET requirement
30 Mbit/s
30 Mbit/s
30 Mbit/s
30 Mbit/s
th(j-a)
th(j-a)
th(j-a)
OL
OH
2
Figure 3
Figure 3
C-bus registers LIMSLICE1 (address C0h) and LIMSLICE2 (address C1h).
= 1 mA
= 0.5 mA
…continued
16 K/W; all characteristics are specified for the default settings; all
16 K/W; all characteristics are specified for the default settings; all
16 K/W; all characteristics are specified for the default settings; all
30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver
CC
CC
2
C-bus registers LIMLOS1CNF (address BDh) and
Min
0
V
0.2
Min
50
V
1
40
18R
-
-
-
-
Min
50
V
40
260
15
15
40
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
20
CC
CC
CC
TZA3012HW
1 -
Typ
-
-
Typ
-
-
50
19.4R
-
-
-
-
1000
Typ
-
50
340
30
30
50
Max
100
V
60
400
60
60
60
Max
0.2
V
Max
1000
V
0.25
60
21R
200
10
10
-
CC
20
CC
CC
0.25 V
Unit
V
V
Unit
mV
V
MHz
ppm
ms
bit
11 of 18
s
s
Unit
mV
ps
ps
ps
%