tza3017hw NXP Semiconductors, tza3017hw Datasheet - Page 15

• Manufacturer Part Number: tza3017hw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-rate Fibre Optic Transmitter
• Manufacturer: NXP Semiconductors

Philips Semiconductors
To allow optimum layout connectivity, the pin designations of the parallel data bus bits can be reversed so that the default
designated pin for the MSB is exchanged with the default designated pin for the LSB. This is implemented by
bit BUSSWAP in I
The highest supported speed for the parallel data bus is 400 Mbits/s. Therefore a multiplexing ratio of 4:1 will support bit
rates of up to 1.6 Gbits/s.
Table 8 Setting multiplexing ratio
Parity checking
The parity checking function verifies the integrity of the incoming data on the parallel data bus. The calculated parity is
compared to the parity expected at pins PARITY and PARITYQ. If these levels do not match, a parity error has occurred
and pin PARERR goes HIGH during the next parallel clock period at pins PICLK and PICLKQ; (see Fig.9).
The calculated parity can be configured to be either odd or even by pin PAREVEN or by bit PARITY in I
register MUXCNF2 (address A0H). Odd parity is configured by either a LOW level at pin PAREVEN or setting
bit PARITY. The default setting for bit PARITY is even parity (logic 0).
2003 May 14
handbook, full pagewidth
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
PIN MUXR1
HIGH
HIGH
LOW
LOW
2
C-bus register MUXCNF2 (address A0H).
PIN MUXR0
HIGH
HIGH
LOW
LOW
PARERR
D00-D15
PARITY
PICLK
PARITY
ERROR
Fig.9 Parity timing.
(REG. MUXCNF1)
BITS MUX
00
01
10
11
15
MULTIPLEXING
RATIO
10:1
16:1
MDB063
4:1
8:1
D06 to D09
D04 to D11
D03 to D12
D00 to D15
TZA3017HW
Product specification
ACTIVE INPUTS
LSB to MSB
2
C-bus