tle4998s Infineon Technologies Corporation, tle4998s Datasheet - Page 12

• Manufacturer Part Number: tle4998s
• Description: Tle4998s/p-programming Guide
• Manufacturer: Infineon Technologies Corporation

5) A program pulse must follow after the frame (output stage is kept disabled).
6) A margin voltage level must follow before the last Vdd clock pulse falling edge (this edge is used for refreshing
2.3
A general data frame sent to the device is shown in
and PO (bit 18) need to be set (in the same way as for the command frame) that the
following conditions are met (bit 0 is the LSB, bit 20 is the MSB):
• bit0 XOR bit2 XOR bit4 XOR …. XOR bit20 = 0
• bit1 XOR bit3 XOR bit5 XOR …. XOR bit19 = 0
Please refer to
shows a general data frame received from the sensor. Instead of a zero bit followed by
two parity bits, the least significant 3 bits of the address used for the readout are
transmitted together with the data. This allows to check the plausibility of the received
data.
Figure 9
Figure 10
2.4
An example parity generator is shown using a pseudo code. The array “framedatabits”
contains the data bits to transmit including the framebits, its index corresponds to 0 ...
LSB and 20 ... MSB.
This parity calculation is valid for command and data frame transmissions:
Application Note
MSB
MSB
1
1
// count framedatabits from 0 (LSB) to 20 (MSB) - this are 21 bits
// bit 0 and 20 are always '1' (framebits)
pe = framedatabit(19);
the EEPROM registers using the margin voltage).
ADR (3 LSBs)
0
O
P
Data Frame Description
Interface Parity Calculation
Data frame (write to device)
Data frame (read from device)
P
E
Chapter 2.4
for a source code example of a parity generator.
10
DATA (16bit)
DATA (16bit)
TLE4998S/P-Programming Guide
Figure
Interface Access Details - Part I
9. The parity bits PE (bit 17)
V 1.1, 2008-08
Figure 10
LSB
LSB
1
1