tmp86c847iug TOSHIBA Semiconductor CORPORATION, tmp86c847iug Datasheet - Page 41

• Manufacturer Part Number: tmp86c847iug
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3. Interrupt Control Circuit
3.1 Interrupt latches (IL15 to IL2)
Internal/External
Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are
maskable.
The interrupt latch is set to “1” by the generation of its interrupt request which requests the CPU to accept its inter-
rupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable
flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is domi-
nated by hardware.
fined instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to
accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting inter-
rupt. All interrupt latches are initialized to “0” during reset.
vidually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt
latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions
such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if inter-
rupt is requested while such instructions are executed.
The TMP86C847IUG has a total of 18 interrupt sources excluding reset, of which 2 source levels are multiplexed.
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors.
Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Inter-
Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1<ATOUT> to “0” (It is set for the “reset request” after reset
Note 3: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to "0" (It is set for the "Reset request" after
An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the unde-
The interrupt latches are located on address 003CH and 003DH in SFR area. Each latch can be cleared to "0" indi-
Interrupt latches are not set to “1” by an instruction.
External
External
External
External
External
External
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
rupt Source Selector (INTSEL)).
is released). For details, see “Address Trap”.
reset is released). For details, see "Watchdog Timer".
(Reset)
INTSWI (Software interrupt)
INTUNDEF (Executed the undefined instruction
interrupt)
INTATRAP (Address trap interrupt)
INTWDT (Watchdog timer interrupt)
INT0
INT1
INTTBT
INTTC1
INT2
INTTC4
INTTC3
INT3
INTSIO
INTRXD
INT4
INTTXD
INT5
INTADC
Interrupt Factors
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Non-maskable
Non-maskable
Non-maskable
Non-maskable
Non-maskable
IMF• EF4 = 1, INT0EN = 1
IMF• EF5 = 1
IMF• EF6 = 1
IMF• EF7 = 1
IMF• EF8 = 1
IMF• EF9 = 1
IMF• EF10 = 1
IMF• EF11 = 1
IMF• EF12 = 1
IMF• EF13 = 1
IMF• EF14 = 1, IL14ER = 0
IMF• EF14 = 1, IL14ER = 1
IMF• EF15 = 1, IL15ER = 0
IMF• EF15 = 1, IL15ER = 1
Enable Condition
Interrupt
Latch
IL10
IL11
IL12
IL13
IL14
IL15
IL2
IL3
IL4
IL5
IL6
IL7
IL8
IL9
–
–
–
TMP86C847IUG
Address
Vector
FFFE
FFFC
FFFC
FFFA
FFEE
FFEC
FFEA
FFE4
FFF8
FFF6
FFF4
FFF2
FFF0
FFE8
FFE6
FFE2
FFE0
Priority
10
11
12
13
14
15
16
2
2
3
4
5
6
7
8
9
1