tmp86c847iug TOSHIBA Semiconductor CORPORATION, tmp86c847iug Datasheet - Page 55
tmp86c847iug
Manufacturer Part Number
tmp86c847iug
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP86C847IUG.pdf
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5. I/O Ports
input data should be externally held until the input data is read from outside or reading should be performed several
times before processing. Figure 5-1 shows input/output timing examples.
timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro-
gram.
port.
The TMP86C847IUG have 5 parallel input/output ports (35 pins) as follows.
Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external
External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This
Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O
Note: The positions of the read and write cycles may vary, depending on the instruction.
Data input
Output strobe
Data output
execution cycle
execution cycle
Port P0
Port P1
Port P2
Port P3
Port P4
nput strobe
nstruction
nstruction
Figure 5-1 Input/Output Timing (Example)
Primary Function
8-bit I/O port
8-bit I/O port
3-bit I/O port
8-bit I/O port
8-bit I/O port
S0
S0
Fetch cycle
Fetch cycle
S1
S1
External interrupt input, serial and timer/counter input/output
External interrupt input, timer/counter input/output, and divider output
Low-frequncy resonator connections, external interrupt input, and
STOP mode release signal input
Analog input, and STOP mode release signal input
S2
S2
S3
S3
Page 47
Ex: LD A, (x)
Ex: LD (x), A
S0
S0
(b) Output timing
(a)
Fetch cycle
Fetch cycle
S1
S1
nput timing
S2
S2
Secondary Functions
S3
S3
S0
S0
Read cycle
Write cycle
S1
S1
S2
S2
S3
S3
TMP86C847IUG
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