tmp86c847iug TOSHIBA Semiconductor CORPORATION, tmp86c847iug Datasheet - Page 69
tmp86c847iug
Manufacturer Part Number
tmp86c847iug
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP86C847IUG.pdf
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7.2.5 Watchdog Timer Reset
Clock
Binary counter
Overflow
INTWDT interrupt request
(WDTCR1<WDTOUT>= "0")
Internal reset
(WDTCR1<WDTOUT>= "1")
WDT reset output
request is generated. When a watchdog timer reset request is generated, the
nal and the internal hardware is reset. The reset time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz).
When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset
Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre-
quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura-
cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
Figure 7-2 Watchdog Timer Interrupt/Reset
1
Write 4E
2
H
to WDTCR2
3
2
17
/fc
0
Page 61
(High-Z)
1
2
19
/fc [s]
2
RESET
3
pin outputs a low-level sig-
A reset occurs
0
TMP86C847IUG
(WDTT=11)
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