tmp88ch40mg TOSHIBA Semiconductor CORPORATION, tmp88ch40mg Datasheet - Page 29

• Manufacturer Part Number: tmp88ch40mg
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Example :Enables interrupts individually and sets IMF
3.2 Interrupt enable register (EIR)
3.2.1 Interrupt master enable flag (IMF)
3.2.2 Individual interrupt enable flags (EF38 to EF3)
maskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog inter-
rupt). Pseudo non-maskable interrupt is accepted regardless of the contents of the EIR.
registers are located on address 003AH, 003BH, 002CH, 002DH and 002AH in SFR area, and they can be read and
written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instruc-
tions).
The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the pseudo non-
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These
While IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual interrupt
enable flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled.
maskable interrupts which follow are disabled temporarily. IMF flag is set to "1" by the maskable interrupt
return instruction [RETI] after executing the interrupt service program routine, and MCU can accept the inter-
rupt again. The latest interrupt request is generated already, it is available immediately after the [RETI] instruc-
tion is executed.
IMF flag is set to "1" only when it performs the pseudo non-maskable interrupt service routine on the interrupt
acceptable status (IMF=1). However, IMF is set to "0" in the pseudo non-maskable interrupt service routine, it
maintains its status (IMF="0").
The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initial-
ized to “0”.
bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit to “0” dis-
ables acceptance. During reset, all the individual interrupt enable flags (EF38 to EF3) are initialized to “0” and
all maskable interrupts are not accepted until they are set to “1”.
The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt.
When an interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the
On the pseudo non-maskable interrupt, the non-maskable return instruction [RETN] is adopted. In this case,
The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction.
Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding
Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear
IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF
or IL (Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute nor-
mally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulat-
ing EF or IL should be executed before setting IMF="1".
DI
SET
CLR
CLR
CLR
EI
:
(EIRL), .5
(EIRL), .6
(EIRH), .4
(EIRD), .0
Page 21
; IMF
; EF5
; EF6
; EF12
; EF24
; IMF
←
←
←
←
←
←
0
1
1
0
0
0
TMP88CH40MG