tmp88ch41ug TOSHIBA Semiconductor CORPORATION, tmp88ch41ug Datasheet - Page 161
tmp88ch41ug
Manufacturer Part Number
tmp88ch41ug
Description
8 Bit Microcontroller Tlcs-870/x Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP88CH41UG.pdf
(240 pages)
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15.4 Transfer Rate
15.5 Data Sampling Method
RXD pin
RXD pin
RT clock
Internal receive data
RT clock
Internal receive data
fer rate are determined as follows:
detected in RXD pin input. RT clock starts detecting “L” level of the RXD pin. Once a start bit is detected, the start
bit, data bits, stop bit(s), and parity bit are sampled at three times of RT7, RT8, and RT9 during one receiver clock
interval (RT clock). (RT0 is the position where the bit supposedly starts.) Bit is determined according to majority
rule (The data are the same twice or more out of three samplings).
The baud rate of UART is set of UARTCRA<BRG>. The example of the baud rate are shown as follows.
When INTTC4 is used as the UART transfer rate (when UARTCRA<BRG> = “110”), the transfer clock and trans-
Transfer clock [Hz] = TC4 source clock [Hz] / TC4DR setting value
Transfer Rate [baud] = Transfer clock [Hz] / 16
The UART receiver keeps sampling input using the clock selected by UARTCRA<BRG> until a start bit is
Table 15-1 Transfer Rate (Example)
BRG
000
001
010
100
101
011
RT0 1
RT0 1
Figure 15-4 Data Sampling Method
Start bit
Start bit
Start bit
Start bit
2
2
3 4
3 4
5 6
5 6
76800 [baud]
(a) Without noise rejection circuit
(b) With noise rejection circuit
16 MHz
38400
19200
9600
4800
2400
Page 151
7
7
8 9 10 11 12 13 14 15 0
8 9 10 11 12 13 14 15 0
Source Clock
Bit 0
38400 [baud]
8 MHz
19200
9600
4800
2400
1200
Bit 0
Bit 0
Bit 0
1
1
2 3
2 3
4 5
4 5
6
6
7 8
7 8
TMP88FH41UG
9 10 11
9 10 11
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