tc94a04afdg TOSHIBA Semiconductor CORPORATION, tc94a04afdg Datasheet - Page 12

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tc94a04afdg

Manufacturer Part Number
tc94a04afdg
Description
1 Chip Audio Digital Processor
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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2.2.2 Setting RAM (sequential)
performed correctly.
The RAMs are set by command data using the IFDI signal.
The first byte after the I
The length of the data field following the RAM address bytes is 2 × n bytes. The address is automatically incremented by 1.
During program running, 1 word of data is written at a time in internal RAM synchronizing with a SYNC signal.
Therefore, when performing continuously two or more write to word, unless it applies more than 1/fs [sec] per 1 word and it sets up, taking in of data is not
At the time of program STOP, it is written in asynchronous.
IFCK
IFDI
CS
(MCU → )
start
A7
A6
A5
A4
32h
A3
2
A2
C address (32h) is a command, which differs for each RAM. The next two bytes contain the start address for each RAM.
A1
A0
HZ
C7
C6
C5
C4
C3
C2
C1
C0
HZ
RA15
RA14
RA13
RA12
RA11
RA10
RA9
RA8
12
HZ
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
HZ
D15
D14
D13
D12
D11
D10
D9
Cn: COMMAND
An: I
RAn: RAM-ADDRESS
Dn: Data
D8
HZ
2
C address
end
TC94A04AFG/AFDG
2005-09-28

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