tc94a04afdg TOSHIBA Semiconductor CORPORATION, tc94a04afdg Datasheet - Page 29

• Manufacturer Part Number: tc94a04afdg
• Description: 1 Chip Audio Digital Processor
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(internal signal)
Rom Dt [17:16]
BootRom Adrs
BTMODE
4.3
4.3.1 Self-Boot Operation at Reset
4.3.2 Self-Boot Operation When Setting Microcontroller
BTIFCK
BTCSN
BTIFDI
RST
FS
Self-Boot Operation
ms when fs = 44.1 kHz) after a reset release is wait period. The boot operation starts at the end of this
period.
is specified to be 0001h, at the time of a reset, the initial value of application will be set up
automatically.
address.
BOOT command (command: 41h) from the microcontroller starts the boot operation with no wait. The
boot operation when set from the microcontroller is the same as the self-boot operation at reset except
that the boot operation can start from any address.
Self-boot operation supports two modes: one for use at reset and for setting the microcontroller.
To enter this mode, set the RST pin to High or send initialized command. The 2048 fs period (46.4
Starting address is fixed to 001h. If the jump address to application to execute at the time of a boot
When you do not boot at the time of a reset, please set JMP (1FFh: data = 301FFh) as 001h.
In this mode, the microcontroller can specify any address and the boot operation starts from that
The BOOT pin can be set to either High or Low. Setting the self-boot ROM start address using the
Boot wait period
Relationship between fs and Wait Period
Figure 3 Boot Timing Chart (at reset)
2048 fs
44.1 kHz
32 kHz
48 kHz
96 kHz
JMP
fs
2
Wait Period
64.0 ms
46.4 ms
42.7 ms
CMD
10
29
DT DT DE
11 12 13 14 15 16
C
D
Boot Time (maximum)
D
8 clock
16.0 ms
11.6 ms
10.7 ms
CMD
C
D
512 fs (max)
Boot period
DE
C
CMD
D
C
TC94A04AFG/AFDG
DT: Data
DE: DataEnd
JMP
JMP
3FF
2005-09-28