tc9447f TOSHIBA Semiconductor CORPORATION, tc9447f Datasheet - Page 11

• Manufacturer Part Number: tc9447f
• Description: Single-chip Audio Digital Signal Processor
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(2)
(2-1) Setting registers
(2-2) Setting RAM (sequential)
When I
When the CS signal is Low, control from the microcontroller is enabled.
The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC9447F loads the
IFDI data on the IFCK signal rising edge. When CS = H, the IFCK and IFDI signals are don't care.
Standard transmission mode 2
The registers are set by command data using the IFDI signal. The first byte is a command, which
differs for each register. The data sent after that are fixed to two bytes. Both command and data
are sent starting from the MSB.
The ACK signal is the acknowledge signal that the TC9447F returns to the microcontroller. As
the ACK signal is open drain output, it must be pulled up outside the pin. The data are loaded
on the rising edge of the IFCK signal.
Note that commands or data that must be switched on the SYNC signal, such as the RUN
command or the IFF flag, must be synchronized with the SYNC signal and loaded on that signal.
The RAMs are set by command data using the IFDI signal. The first byte is a command, which
differs for each RAM. The next two bytes contain the start address for the RAM written.
The length of the data field following the RAM address bytes is 2 × n bytes. The address is
automatically incremented by 1.
2
CS = L, data can be transmitted or received in Standard Transmission mode.
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2002-02-05
TC9447F