tc9447f TOSHIBA Semiconductor CORPORATION, tc9447f Datasheet - Page 14

• Manufacturer Part Number: tc9447f
• Description: Single-chip Audio Digital Signal Processor
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(3)
(3-1) Setting registers
(3-2) Setting RAM (sequential)
I
When I
When the CS signal is Low, control from the microcontroller is enabled.
In I
The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC9447F loads the
IFDI data on the IFCK signal rising edge. When CS = H, the IFCK and IFDI signals are don't care.
2
C bus mode
2
The registers are set by command data using the IFDI signal. The first byte after the I
(32h) is a command, which differs for each register. The data sent after that are fixed to two bytes.
Both command and data are sent starting from the MSB in I
The ACK pin cannot be used in I
using data signals in I
Note that commands or data that must be switched on the SYNC signal, such as the RUN
command or the IFF flag, must be synchronized with the SYNC signal and loaded on that signal.
The RAMs are set by command data using the IFDI signal.
The first byte after the I
bytes contain the start address for the RAM to be written to. The length of the data field following
the RAM address bytes is 2 × n bytes. The address is automatically incremented by 1.
C mode, the CS signal can be used fixed to L.
2
CS = H, data can be transmitted or received in Standard Transmission mode.
2
C format. The data are loaded internally every two bytes.
2
C address (32h) is a command, which differs for each RAM. The next two
2
C format. However, the acknowledge signal can be read by
14
2
C format.
2002-02-05
TC9447F
2
C address