hcs112ms Intersil Corporation, hcs112ms Datasheet

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hcs112ms

Manufacturer Part Number
hcs112ms
Description
Radiation Hardened Dual Jk Flip-flop
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
• Input Current Levels Ii
Description
The Intersil HCS112MS is a Radiation Hardened dual JK
flip-flop with set and reset. The output changes state on the
negative going transition of the clock pulse. Set and reset
are accomplished asynchronously by a logic low input level.
The HCS112MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS112MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCS112DMSR
HCS112KMSR
HCS112D/Sample
HCS112K/Sample
HCS112HMSR
Bit-Day (Typ)
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
RAD (Si)/s
-55
-55
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
/mg
-9
o
o
C
C
Errors/
11
Pinouts
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
GND
CP1
SCREENING LEVEL
QA
QA
QB
KA
SA
JA
HCS112MS
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
16 LEAD CERAMIC DUAL-IN-LINE
16 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
CP1
QA
QA
QB
KA
SA
JA
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
TOP VIEW
TOP VIEW
Radiation Hardened
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
Dual JK Flip-Flop
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
Spec Number
VCC
RA
RB
CPB
KB
JB
SB
QB
File Number
PACKAGE
VCC
RA
RB
CPB
KB
JB
SB
QB
518830
3558.1

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hcs112ms Summary of contents

Page 1

... The HCS112MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS112MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER ...

Page 2

... High Steady State Low Steady State Immaterial, = High-to-Low Transition * Output States Unpredictable if S and R Go High Simultaneously after Both being Low at the Same Time HCS112MS TRUTH TABLE ...

Page 3

... VIL = 1.35V (Note 3) NOTES: 1. All voltages referenced to device GND. 2. Force/Measure Functions may be interchanged. 3. For functional tests, VO 4.0V is recognized as a logic “1”, and VO Specifications HCS112MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . ...

Page 4

... The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. Specifications HCS112MS GROUP (NOTES 1, 2) ...

Page 5

... AC measurements assume RL = 500 , CL = 50pF, Input 3ns, VIL = GND, VIH = 3V. 3. For functional tests VO 4.0V is recognized as a logic “1”, and VO TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 PARAMETER ICC IOL/IOH Specifications HCS112MS (NOTES 1, 2) CONDITIONS TEMPERATURE 0.5V is recognized as a logic “0”. GROUP B SUBGROUP ...

Page 6

... Each pin except VCC and GND will have a resistor of 1K OPEN NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCS112MS TABLE 6. APPLICABLE SUBGROUPS METHOD GROUP A SUBGROUPS 100%/5004 ...

Page 7

... Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HCS112MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...

Page 8

... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 HCS112MS Pulse Width, Setup, Hold Timing Diagram Negative Edge Trigger and AC Load Circuit INPUT VIH VS TPHL ...

Page 9

... Metallization Mask Layout JA (3) SA (4) QA (5) QA (6) QB (7) NOTE: The die diagram is a generic plot from a similar HCS device intended to indicate approximate die size and bond pad location. The mask series for the HCS112 is TA14341A. HCS112MS HCS112MS KA CP1 VCC (2) (1) (16) (8) (9) ...

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