tza1000 NXP Semiconductors, tza1000 Datasheet - Page 7

• Manufacturer Part Number: tza1000
• Description: Qic Read-write Amplifier
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Bias and magnetic feedback circuit
This circuit can be used to generate AC and DC bias
currents (for a yoke-type MR head, for instance).
The DC bias output voltage is programmable
between 0 and 1.4 V, with 5-bit resolution (see Table 3).
The DC current generated is this voltage divided by the
total bias resistance (head coil + total series resistance).
The AC signal input to the circuit can be switched to the
preamplifier output (see Table 10). In this way, magnetic
feedback inside the head can be achieved. This limits
head distortion, and prevents head saturation from large
tape signals, like QIC 80 recordings.
The open loop gain of the feedback loop depends on head
sensitivity, the selected sense current (see Table 15), and
the selected preamplifier gain (see Table 11). The values
of the external resistors connected in series with the bias
conductor can be used to set the gain. For loop stability at
high frequencies, the bandwidth of the magnetic feedback
amplifier is limited to 5 MHz.
In closed loop mode, the effective cut-off frequency for the
playback signals will increase with the feedback factor. For
this reason the read signal can be taken from the output of
the bias circuit.
To prevent loop instability at low frequencies, the
preamplifier input capacitors should be chosen such that
the cut-off frequency at that point is well above, or well
below, the internal cut-off frequency of the AC coupling
between the preamplifier and the bias circuit (input
impedance of the preamplifier is typically 2 k ).
The maximum (peak AC) current that the bias circuit can
deliver can be adjusted to achieve an optimum balance
between required current range and power consumption
(see Table 3). The AC circuit is switched off when the
TZA1000 is writing, and the maximum current is switched
to 10 mA. This limits power dissipation during writing.
Test generator
This circuit generates a test signal with a frequency
that of the signal at the CLK input (pin 15). By switching the
AC input of the bias circuit to the internal test generator
(see Table 10), the read channel can be tested.
The differential output value is typically 100 mV (p-p).
This facility can also be used to adjust the DC bias voltage
while monitoring the signal at the read element in the head.
The optimum DC bias level setting is just before the output
from the read head reaches its peak.
1998 Mar 17
QIC read-write amplifier
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Write circuit
The write circuit is a differential current source that can
generate a near rail-to-rail output voltage to get the
shortest current transition time. Writing is enabled when
WGATE is LOW. The polarity of the current depends on
the WD input pin. The WDM bit in the control register
determines the write signal mode: WD (Non-Return to
Zero) or WDI (Return to Zero; see Table 14). When WDI
mode is selected, the polarity of the write current is
reversed at every falling edge of the WD input. When WD
mode is selected, the polarity of the write current is
reversed when the polarity of WD changes. The write
current is programmable between 0 and 125 mA, with
7-bit resolution (see Table 14).
The IC is specified for a write current of up to 100 mA.
Overshoot caused by an inductive load can be minimized
by means of a single external resister local to the IC.
Write unsafe detector
The write unsafe detector will detect an open write coil, or
one shorted to ground. The circuit is enabled only while the
TZA1000 is writing. A resistance to GND or V
than 10 , or a series resistance greater that about 300
will be detected (these values are write-current
dependant). If an error occurs, the WUS status bit is set.
This bit can be read via the serial interface. The WUS bit
will remain set until the status byte is read.
Power fail detector
The power fail detector will detect a low voltage on the 5 V
(V
3.75 V for V
detected if the voltage is below the threshold for 1 s or
longer. If a 5 V power failure occurs, the status bit PF5 is
set. If a 12 V power failure occurs, the status bit PF12 is
set. These bits can be read via the serial interface, and will
remain HIGH until the status byte is read.
When a 5 V power failure occurs, the RESET output goes
LOW and the write circuit is disabled (in addition to PF5
being set). The RESET output has an internal 18 k pull
down resistor to guarantee a LOW level at the output even
when a power failure occurs. During normal operation, the
RESET pin should not be held LOW by an external circuit,
since this will switch the IC into test mode.
DD1
) or 12 V (V
DD1
and 9 V for V
DD3
) supply lines. The thresholds are
DD3
. A power failure is
Preliminary specification
TZA1000
DD
of less
,