attiny25v ATMEL Corporation, attiny25v Datasheet - Page 147

• Manufacturer Part Number: attiny25v
• Description: Microcontroller With 2/4/8k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

19.5
19.6
19.6.1
19.6.2
2586K–AVR–01/08
EEPROM Write Prevents Writing to SPMCSR
Reading Lock, Fuse and Signature Data from Software
Reading Lock Bits from Firmware
Reading Fuse Bits from Firmware
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read fuse and lock bits from firmware. In addition, firmware can also read data
from the device signature imprint table (see
Note:
Issuing an LPM instruction within three CPU cycles after RFLB and SELFPRGEN bits have
been set in SPMCSR will return lock bit values in the destination register. The RFLB and SELF-
PRGEN bits automatically clear upon completion of reading the lock bits, or if no LPM instruction
is executed within three CPU cycles, or if no SPM instruction is executed within four CPU cycles.
When RFLB and SELFPRGEN are cleared LPM functions normally.
To read the lock bits, follow the below procedure:
If successful, the contents of the destination register are as follows.
See section
The algorithm for reading fuse bytes is similar to the one described above for reading lock bits,
only the addresses are different. To read the Fuse Low Byte (FLB), follow the below procedure:
If successful, the contents of the destination register are as follows.
Refer to
Bit
Rd
Bit
Rd
1. Load the Z-pointer with 0x0001.
2. Set RFLB and SELFPRGEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Read the lock bits from the LPM destination register.
1. Load the Z-pointer with 0x0000.
2. Set RFLB and SELFPRGEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Read the FLB from the LPM destination register.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unpro-
grammed, will be read as one.
Table 20-5 on page 153
“Program And Data Memory Lock Bits” on page 151
FLB7
7
–
7
FLB6
6
–
6
for a detailed description and mapping of the Fuse Low Byte.
FLB5
5
–
5
FLB4
page
4
–
4
153).
FLB3
3
–
3
FLB2
2
–
2
for more information.
ATtiny25/45/85
FLB1
LB2
1
1
FLB0
LB1
0
0
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