pic32mx320f032h Microchip Technology Inc., pic32mx320f032h Datasheet - Page 23

• Manufacturer Part Number: pic32mx320f032h
• Description: 64/100-pin General Purpose And Usb 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

TABLE 3-1:
The MIPS architecture defines that the result of a mul-
tiply or divide operation be placed in the HI and LO reg-
isters. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the general purpose register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the
primary register file instead of the HI/LO register pair.
By avoiding the explicit MFLO instruction, required
when using the LO register, and by supporting multiple
destination registers, the throughput of multiply-inten-
sive operations is increased.
Two other instructions, multiply-add (MADD) and multi-
ply-subtract (MSUB), are used to perform the multiply-
accumulate and multiply-subtract operations. The
MADD instruction multiplies two numbers and then adds
TABLE 3-2:
© 2009 Microchip Technology Inc.
Register
Number
MULT/MULTU, MADD/MADDU,
0-6
10
11
12
12
12
12
13
14
15
15
16
16
16
16
7
8
9
MSUB/MSUBU
Register
Name
Reserved
HWREna
BadVAddr
Count
Reserved
Compare
Status
IntCtl
SRSCtl
SRSMap
Cause
EPC
PRId
EBASE
Config
Config1
Config2
Config3
DIV/DIVU
Opcode
MUL
(1)
(1)
(1)
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
COPROCESSOR 0 REGISTERS
(1)
(1)
PIC32MX3XX/4XX FAMILY CORE HIGH-PERFORMANCE INTEGER
(1)
(1)
(1)
(1)
Function
Reserved in the PIC32MX3XX/4XX Family core
Enables access via the RDHWR instruction to selected hardware registers
Reports the address for the most recent address-related exception
Processor cycle count
Reserved in the PIC32MX3XX/4XX Family core
Timer interrupt control
Processor status and control
Interrupt system status and control
Shadow register set status and control
Provides mapping from vectored interrupt to a shadow set
Cause of last general exception
Program counter at last exception
Processor identification and revision
Exception vector base register
Configuration register
Configuration register 1
Configuration register 2
Configuration register 3
Operand Size (mul rt) (div rs)
Preliminary
16 bits
32 bits
16 bits
32 bits
16 bits
24 bits
32 bits
8 bits
the product to the current contents of the HI and LO
registers. Similarly, the MSUB instruction multiplies two
operands and then subtracts the product from the HI
and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
3.2.3
In the MIPS architecture, CP0 is responsible for the vir-
tual-to-physical address translation, the exception con-
trol system, the processor’s diagnostics capability, the
operating modes (kernel, user, and debug), and
whether interrupts are enabled or disabled. Configura-
tion information, such as presence of options like
MIPS16e, is also available by accessing the CP0 reg-
isters, listed in Table 3-2.
PIC32MX3XX/4XX
SYSTEM CONTROL
COPROCESSOR (CP0)
Latency
12
19
26
33
1
2
2
3
DS61143F-page 21
Repeat Rate
18
25
32
11
1
1
2
2