at91sam7x256 ATMEL Corporation, at91sam7x256 Datasheet - Page 15

• Manufacturer Part Number: at91sam7x256
• Description: Preliminary Summary
• Manufacturer: ATMEL Corporation

7. Processor and Architecture
7.1
7.2
7.3
6120ES–ATARM–08-Oct-07
ARM7TDMI Processor
Debug and Test Features
Memory Controller
• RISC processor based on ARMv4T Von Neumann architecture
• Two instruction sets
• Three-stage pipeline architecture
• Integrated embedded in-circuit emulator
• Debug Unit
• IEEE1149.1 JTAG Boundary-scan on all digital pins
• Programmable Bus Arbiter
• Address decoder provides selection signals for
• Abort Status Registers
• Misalignment Detector
• Remap Command
– Runs at up to 55 MHz, providing 0.9 MIPS/MHz
– ARM high-performance 32-bit instruction set
– Thumb high code density 16-bit instruction set
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Two watchpoint units
– Test access port accessible through a JTAG protocol
– Debug communication channel
– Two-pin UART
– Debug communication channel interrupt handling
– Chip ID Register
– Handles requests from the ARM7TDMI, the Ethernet MAC and the Peripheral DMA
– Three internal 1 Mbyte memory areas
– One 256 Mbyte embedded peripheral area
– Source, Type and all parameters of the access leading to an abort are saved
– Facilitates debug by detection of bad pointers
– Alignment checking of all data accesses
– Abort generation in case of misalignment
– Remaps the SRAM in place of the embedded non-volatile memory
– Allows handling of dynamic exception vectors
AT91SAM7X512/256/128 Preliminary Summary
Controller
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