at91sam7x256 ATMEL Corporation, at91sam7x256 Datasheet - Page 37

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at91sam7x256

Manufacturer Part Number
at91sam7x256
Description
Preliminary Summary
Manufacturer
ATMEL Corporation
Datasheet

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10.12 Pulse Width Modulation Controller
10.13 USB Device Port
6120ES–ATARM–08-Oct-07
Table 10-4.
TC Clock input
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
• Each channel is user-configurable and contains:
• Five internal clock inputs, as defined in
• Four channels, one 16-bit counter per channel
• Common clock generator, providing thirteen different clocks
• Independent channel programming
• USB V2.0 full-speed compliant,12 Mbits per second
• Embedded USB V2.0 full-speed transceiver
• Embedded 1352-byte dual-port RAM for endpoints
• Six endpoints
– Pulse generation
– Delay timing
– Pulse Width Modulation
– Up/down capabilities
– Three external clock inputs
– Two multi-purpose input/output signals
– Two global registers that act on all three TC channels
– One Modulo n counter providing eleven clocks
– Two independent linear dividers working on modulo n counter outputs
– Independent enable/disable commands
– Independent clock selection
– Independent period and duty cycle, with double buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
– Endpoint 0: 8 bytes
– Endpoint 1 and 2: 64 bytes ping-pong
– Endpoint 3: 64 bytes
– Endpoint 4 and 5: 256 bytes ping-pong
– Ping-pong Mode (two memory banks) for bulk endpoints
AT91SAM7X512/256/128 Preliminary Summary
Timer Counter Clocks Assignment
Table 10-4
Clock
MCK/2
MCK/8
MCK/32
MCK/128
MCK/1024
37

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