at32ap7000 ATMEL Corporation, at32ap7000 Datasheet
at32ap7000
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at32ap7000 Summary of contents
Page 1
... On-Chip Debug System – Nexus Class 3 – Full speed, non-intrusive data and program trace – Runtime control and JTAG interface • Package/Pins – AT32AP7000: 256-ball CTBGA 1.0 mm pitch/160 GPIO pins • Power supplies – 1.65V to1.95V VDDCORE – 3.0V to 3.6V VDDIO ® 32 32-Bit Microcontroller 2 © ...
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... AT32AP7000 also features an onboard LCD Controller, supporting single and double scan monochrome and color passive STN LCD modules and single scan active TFT LCD modules. On monochrome STN displays gray shades are supported using a time-based dither- ing algorithm and Frame Rate Control (FRC) method ...
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... AT32AP7000 integrates a class 3 Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. The C-compiler is closely linked to the architecture and is able to utilize code optimization fea- tures, both for size and speed. 32003KS–AVR32–10/07 ...
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... DMA CONTROLLER AUDIO BITSTREAM DAC MULTIMEDIA CARD INTERFACE AC97 CONTROLLER POWER MANAGER CLOCK GENERATOR CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER TIMER/COUNTER 0/1 EXTERNAL INTERRUPT CONTROLLER AT32AP7000 PIXEL COPROCESSOR VSYNC, DATA HSYNC, CACHE LCD PWR, PCLK, CONTRO MODE, LLER DVAL, CC, DATA[22..0], GPL[7.. DMA M ...
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... Supports packed and planar input and output formats. • Supports subsampled input color spaces (i.e 4:2:2, 4:2:0). • Configurable Filter Coefficients. • Throughput of one sample per cycle for a 9-tap FIR filter. • Can use the built-in accumulator to extend the FIR filter to more than 9-taps. • Can be used for bilinear/bicubic interpolations. AT32AP7000 5 ...
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... HSB bus matrix with 10 Masters and 8 Slaves handled – Handles Requests from the CPU Icache, CPU Dcache, HSB bridge, HISI, USB 2.0 Controller, LCD Controller, Ethernet Controller 0, Ethernet Controller 1, DMA Controller 0, DMA Controller 1, and to internal SRAM 0, internal SRAM EBI and, USB. 32003KS–AVR32–10/07 AT32AP7000 6 ...
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... Power Manager. The figure identifies the number of master and slave interfaces of each module connected to the HSB bus, and which DMA controller is connected to which peripheral. 32003KS–AVR32–10/07 AT32AP7000 Figure 4-1 on page 13. All modules connected to the accessed default ...
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... PA08 GND PA13 PA10 PA12 PA17 PA15 PD14 PA21 PD11 PD16 PA23 PD13 PD17 PA24 PD12 PD15 AT32AP7000 BOTTOM VIEW PE02 AGNDPLL PLL0 AVDDOSC PE00 PLL1 GND AGNDOSC PE01 XOUT32 AVDDPLL XIN0 ...
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... PX22 PX23 PX24 PE24 PX38 PX18 PE20 PX08 PX34 PE22 PX06 PX11 PE21 PX09 PB30 PE23 PX07 PB29 PE19 PX10 PX12 AT32AP7000 PB11 GND VDDIO PB10 PC17 PC16 PB09 PB07 PB08 PB05 PB04 PB06 PB01 VDDIO PB02 PX43 PX40 PX45 ...
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... Power Power Power Power Power Power Ground Ground Ground Ground Clocks, Oscillators, and PLL’s Analog Analog Analog JTAG Input Input Output Input Input Auxiliary Port - AUX Output Output Output Input AT32AP7000 Active Level Comments 1.65 to 1.95 V 1.65 to 1.95 V 1.65 to 1.95 V 1.65 to 1.95 V 3.0 to 3.6V Low Low 10 ...
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... External Interrupt Controller - EIC Input Input AC97 Controller - AC97C Input Output Output Input Audio Bitstream DAC - ABDAC Output Output Ethernet MAC - MACB0, MACB1 Input Input Output I/O Input Input Input Input Output Output AT32AP7000 Active Level Comments Low Low Low Low Low 11 ...
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... External Bus Interface - EBI I/O Output Output Output Output Output I/O Output Output Output Output Input Output Output Output Output Output Output Output Output Image Sensor Interface - ISI Input Input Input AT32AP7000 Comments Low Low Low Low Low Low Low Low Low Low Low Low Low 12 ...
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... Master Out Slave In NPCS0 - NPCS3 SPI Peripheral Chip Select 32003KS–AVR32–10/07 LCD Controller - LCDC MultiMedia Card Interface - MCI Parallel Input/Output - PIOA, PIOB, PIOC, PIOD, PIOE PS2 Interface - PSIF Serial Peripheral Interface - SPI0, SPI1 AT32AP7000 Active Type Level Comments Input Output Input Output ...
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... CLK Clock CTS Clear To Send RTS Request To Send RXD Receive Data 32003KS–AVR32–10/07 Type Output Synchronous Serial Controller - SSC0, SSC1, SSC2 Output DMA Controller - DMACA Timer/Counter - TIMER0, TIMER1 Two-wire Interface - TWI Output AT32AP7000 Active Level Comments I/O Input I/O I/O I/O Input I/O I/O I/O I/O I/O I/O Input Input ...
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... Full Speed USB Interface Data + VBG USB bandgap 32003KS–AVR32–10/07 Type Output Pulse Width Modulator - PWM Output USB Interface - USBA Analog Analog Analog Analog Analog AT32AP7000 Active Level Comments Connected to a 6810 Ohm ± 0.5% resistor to gound and capacitor to ground. 15 ...
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... Power Considerations 4.1 Power Supplies The AT32AP7000 has several types of power supply pins: • VDDCORE pins: Power the core, memories, and peripherals. Voltage is 1.8V nominal. • VDDIO pins: Power I/O lines. Voltage is 3.3V nominal. • VDDPLL pin: Powers the PLL. Voltage is 1.8V nominal. • VDDUSB pin: Powers the USB. Voltage is 1.8V nominal. ...
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... All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, I/O lines default as inputs with pull-up resistors enabled, except when indicated otherwise in the column “Reset State” of the PIO Controller multiplexing tables. 32003KS–AVR32–10/07 AT32AP7000 17 ...
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... Physical Memory Map The system bus is implemented as an HSB bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AT32AP7000 by default uses segment translation, as described in the AVR32 Architecture Manual. The 32 bit physical address space is mapped as follows: Table 6-1 ...
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... Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 32003KS–AVR32–10/07 HSB masters HSB slaves AT32AP7000 CPU Dcache CPU Icache HSB-HSB Bridge ISI DMA USBA DMA LCD Controller DMA Ethernet MAC0 DMA Ethernet MAC1 DMA DMAC Master Interface 0 DMAC Master Interface 1 ...
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... Synchronous Serial Controller - SSC0 SSC1 Synchronous Serial Controller - SSC1 SSC2 Synchronous Serial Controller - SSC2 PIOA Parallel Input/Output 2 - PIOA PIOB Parallel Input/Output 2 - PIOB PIOC Parallel Input/Output 2 - PIOC PIOD Parallel Input/Output 2 - PIOD AT32AP7000 Bus HSB HSB HSB ...
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... ABDAC Audio Bitstream DAC - ABDAC MCI MultiMedia Card Interface - MCI AC97C AC97 Controller - AC97C ISI Image Sensor Interface - ISI USBA USB Configuration Interface - USBA SMC Static Memory Controller - SMC AT32AP7000 Bus ...
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... Each group can have interrupt request signals. All interrupt signals in the same group share the same autovector address and priority level. Refer to the documentation for the individ- ual submodules for a description of the semantic of the different interrupt requests. The interrupt request signals in AT32AP7000 are connected to the INTC as follows: Table 7-2. Group ...
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... Interrupt Request Signal Map Line Signal 0 SSC2 0 PIOA 0 PIOB 0 PIOC 0 PIOD 0 PIOE 0 PSIF 0 EIC0 1 EIC1 2 EIC2 3 EIC3 RTC 0 TC00 1 TC01 2 TC02 0 TC10 1 TC11 2 TC12 0 PWM 0 MACB0 0 MACB1 0 ABDAC 0 MCI 0 AC97C 0 ISI 0 USBA 0 EBI AT32AP7000 23 ...
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... MCI TX ABDAC TX AC97C CHANNEL A RX AC97C CHANNEL A TX AC97C CHANNEL B RX AC97C CHANNEL B TX EXTERNAL DMA REQUEST 0 EXTERNAL DMA REQUEST 1 EXTERNAL DMA REQUEST 2 EXTERNAL DMA REQUEST 3 32003KS–AVR32–10/07 Hardware Handshaking Connection AT32AP7000 Hardware Handshaking Interface ...
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... TIMER_CLOCK5 External XC0 XC1 XC2 Internal TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 External XC0 XC1 XC2 USART clock connections Source Name Internal CLK_DIV AT32AP7000 Connection clk_osc32 clk_pbb / 4 clk_pbb / 8 clk_pbb / 16 clk_pbb / 32 See Section 7.7 clk_osc32 clk_pbb / 4 clk_pbb / 8 clk_pbb / 16 clk_pbb / 32 See Section 7.7 Connection clk_pba / 8 25 ...
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... SPI clock connections Source Internal External Interrupt Pin Mapping Nexus OCD AUX port connections AXS=0 EVTI_N PB09 PB08 PB07 PB06 PB05 PB04 PB03 PB02 PB01 PB00 AT32AP7000 Name Connection CLK_DIV clk_pba / 32 Connection PB24 PB25 PB26 PB27 PB28 AXS=1 EVTI_N PC18 PC14 PC12 PC11 ...
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... Peripheral Multiplexing on IO lines The AT32AP7000 features five PIO controllers, PIOA to PIOE, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two peripheral functions The tables in the following pages define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers ...
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... PB24 NMI_N PB25 EXTINT0 PB26 EXTINT1 PB27 EXTINT2 PB28 EXTINT3 PB29 PM - GCLK[3] PB30 PM - GCLK[4] AT32AP7000 TC1 - B2 TC1 - CLK1 TC1 - CLK2 Peripheral B SPI1 - MISO SPI1 - MOSI SPI1 - NPCS[0] SPI1 - NPCS[1] SPI1 - NPCS[2] SPI1 - SCK MCI - CMD[1] MCI - DATA[4] MCI - DATA[5] MCI - DATA[6] ...
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... LCDC - PWR PC26 LCDC - DATA[0] PC27 LCDC - DATA[1] PC28 LCDC - DATA[2] PC29 LCDC - DATA[3] PC30 LCDC - DATA[4] PC31 LCDC - DATA[5] AT32AP7000 Peripheral B DMACA - DMARQ[2] DMACA - DMARQ[3] MACB1 - COL MACB1 - CRS MACB1 - RX_CLK MACB1 - TX_ER MACB1 - TXD[2] MACB1 - TXD[3] MACB1 - RXD[2] MACB1 - RXD[3] 29 ...
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... PE06 EBI - DATA[22] PE07 EBI - DATA[23] PE08 EBI - DATA[24] PE09 EBI - DATA[25] PE10 EBI - DATA[26] PE11 EBI - DATA[27] AT32AP7000 Peripheral B MACB1 - MDIO MACB1 - MDC MACB1 - RX_DV MACB1 - RX_ER MACB1 - RXD[1] MACB1 - RXD[0] MACB1 - TX_EN MACB1 - TX_CLK MACB1 - TXD[0] MACB1 - TXD[1] MACB1 - SPEED ...
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... EBI - ADDR[24] PE18 EBI - ADDR[25] PE19 EBI - CFCE1 PE20 EBI - CFCE2 PE21 EBI - NCS[4] PE22 EBI - NCS[5] PE23 EBI - CFRNW PE24 EBI - NWAIT PE25 EBI - NCS[2] AT32AP7000 LCDC - DATA[12] LCDC - DATA[16] LCDC - DATA[17] LCDC - DATA[18] LCDC - DATA[19] LCDC - DATA[20] LCDC - DATA[21] 31 ...
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... Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. 32003KS–AVR32–10/ – – – – – – – – – EBI_CS4A EBI_CS3A AT32AP7000 – – – – – – – – EBI_DBPUC – EBI_CS1A - 32 ...
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... EBI - DATA[14] EBI - DATA[15] EBI - ADDR[0] EBI - ADDR[1] EBI - ADDR[2] EBI - ADDR[3] EBI - ADDR[4] EBI - ADDR[5] EBI - ADDR[6] EBI - ADDR[7] EBI - ADDR[8] EBI - ADDR[9] EBI - ADDR[10] EBI - ADDR[11] EBI - ADDR[12] EBI - ADDR[13] EBI - ADDR[14] EBI - ADDR[15] AT32AP7000 The pull-up resistors are 33 ...
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... EBI - ADDR[18] EBI - ADDR[19] EBI - ADDR[20] EBI - ADDR[21] EBI - ADDR[22] EBI - NCS[0] EBI - NCS[1] EBI - NCS[3] EBI - NRD EBI - NWE0 EBI - NWE1 EBI - NWE3 EBI - SDCK EBI - SDCKE EBI - RAS EBI - CAS EBI - SDWE EBI - SDA10 EBI - NANDOE EBI - NANDWE AT32AP7000 34 ...
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... Programming Facilities – Word, Half-word, Byte Access – Automatic Page Break When Memory Boundary Has Been Reached – Multibank Ping-pong Access – Timing Parameters Specified by Software – Automatic Refresh Operation, Refresh Rate is Programmable 32003KS–AVR32–10/07 AT32AP7000 TM TM and CompactFlash Support TM Support ...
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... The chip select line may be left active to speed up transfers on the same device 7.8.6 Two-wire Interface • Compatibility with standard two-wire serial memory • One, two or three bytes for slave address • Sequential read/write operations 32003KS–AVR32–10/07 AT32AP7000 ™ Devices with 8- or 16-bit Data Path. 36 ...
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... One RX and one TX channel for data transfers, connected to the DMACA • Time Slot Assigner allowing to assign time slots to a channel • Channels support mono or stereo bit sample length - Variable sampling rate AC97 Codec Interface (48KHz and below) 32003KS–AVR32–10/07 AT32AP7000 37 ...
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... Two independent Linear Dividers working on modulo n counter outputs • Independent channel programming – Independent Enable Disable Commands – Independent Clock – Independent Period and Duty Cycle, with Double Bufferization – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 32003KS–AVR32–10/07 AT32AP7000 38 ...
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... Controller for management of virtual Frame Buffer – Allows management of frame buffer larger than the screen size and moving the view over this virtual frame buffer • Automatic resynchronization of the frame buffer pointer to prevent flickering • Configurable coefficients with flexible fixed-point representation. 32003KS–AVR32–10/07 AT32AP7000 39 ...
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... Support for ITU-R BT.656-4 SAV and EAV synchronization • Vertical and horizontal resolutions up to 2048 x 2048 • Preview Path up to 640*480 • Support for packed data formatting for YCbCr 4:2:2 formats • Preview scaler to generate smaller size image 50 • Programmable frame capture rate 32003KS–AVR32–10/07 AT32AP7000 40 ...
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... Boot Sequence This chapter summarizes the boot sequence of the AT32AP7000. The behaviour after power-up is controlled by the Power Manager. 8.1 Starting of clocks After power-up, the device will be held in a reset state by the Power-On Reset (POR) circuitry until the voltage has reached the power-on reset rising threshold value (see Electrical Character- istics for details) ...
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... Ordering Information Figure 9-1. Ordering Information Ordering Code AT32AP7000-CTUR AT32AP7000-CTUT 32003KS–AVR32–10/07 Package Package Type CTBGA256 Green CTBGA256 Green AT32AP7000 Temperature Packing Operating Range Reel Industrial (-40°C to 85°C) Tray Industrial (-40°C to 85°C) 42 ...
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... MCI FIFO in an inconsistent state. Subsequent reads and writes will not function properly. Fix/Workaround Always transfer 12 or more bytes at a time. If less than 12 bytes are transferred, the only recovery mechanism is to perform a software reset of the MCI. 32003KS–AVR32–10/07 AT32AP7000 43 ...
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... Consecutive periods are 0x0001, 0x0002, ..., period 11. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 32003KS–AVR32–10/07 AT32AP7000 44 ...
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... TDRE flag by writing in the SPI_TDR the SPI is disabled during a PDC transfer, the PDC will continue to write data in the SPI_TDR (as TDRE keeps High) till its buffer is empty, and all data written after the disable command is lost. 32003KS–AVR32–10/07 AT32AP7000 45 ...
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... There UNDERRUN flag available, therefore in slave mode there is no way to be informed of a character lost in transmission. Fix/Workaround PDC/PDCA transfers: None. Manual transfers (no PDC and TX slave only): Read the RHR every time the THR is written. The OVRS flag of the status register will track any UNDERRUN on the TX side. 32003KS–AVR32–10/07 AT32AP7000 46 ...
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... MB using these lines will fail, as the flash will be accessed with these address bits set. Fix/Workaround Add external pulldown resistors (5 kΩ) on these lines if booting from a flash larger than 8 MB using these address lines. 32003KS–AVR32–10/07 AT32AP7000 47 ...
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... AVR32_PM.rcause register for WDT reset and use a GPIO pin to reset the system. This method requires that one of the GPIO pins are available and connected externally to the 32003KS–AVR32–10/07 AT32AP7000 48 ...
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... Transfer (CSAAT the behavior of the Chip Select will be unpredictable. Fix/Workaround - Do not use CSAAT = Use GPIO to control Chip Select lines - Select PS=1 and store data for PCS and LASTXFER for each data in transmit buffer. 4. MMC data write operation with less than 12 bytes is impossible. 32003KS–AVR32–10/07 AT32AP7000 49 ...
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... Writing to the MERIT-bit in the LCD Interrupt Test Register (ITR) does not cause an interrupt as intended. The MERIC-bit in the LCD Interrupt Clear Register (ICR) cannot be written. This means that if the MERIS-bit in ISR is set, it cannot be cleared. Fix/Workaround Memory error interrupt should not be used. 32003KS–AVR32–10/07 AT32AP7000 50 ...
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... Peripherals connected to wrong clock signal The frequency of the divided clocks for the SPI and the USART is set by the clock configura- tion for peripheral bus B (PBB) and not by peripheral bus A. Fix/Workaround Use clock settings for PBB for the SPI and USART. 32003KS–AVR32–10/07 AT32AP7000 51 ...
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... The transmitting UART must set timeguard greater than 0. 23. USART - Manchester encoding/decoding is not working. Manchester encoding/decoding is not working. Fix/Workaround Do not use manchester encoding. 32003KS–AVR32–10/07 mov r11, lo(0x24002000) orh r11, hi(0x24002000) ld.w r11, r11[0] mov r10, lo(0x24000000) orh r10, hi(0x24000000) ld.w r10, r10[0] AT32AP7000 //access first RAM //access second RAM 52 ...
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... AUTO_REFRESH sequence. Fix/Workaround Set the value of TRAS field in user interface with TRC+1. 29. SPI - No TX UNDERRUN flag available There UNDERRUN flag available, therefore in slave mode there is no way to be informed of a character lost in transmission. Fix/Workaround 32003KS–AVR32–10/07 AT32AP7000 53 ...
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... MB using these lines will fail, as the flash will be accessed with these address bits set. Fix/Workaround Add external pulldown resistors (5 kΩ) on these lines if booting from a flash larger than 8 MB using these address lines. 32003KS–AVR32–10/07 AT32AP7000 54 ...
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... AVR32_PM.rcause register for WDT reset and use a GPIO pin to reset the system. This 32003KS–AVR32–10/07 AT32AP7000 55 ...
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... Configure the MCI Mode Register (MR) to accept 8-bit data input by writing bit 13 (FBYTE), and transfer each byte of the transmit data to TDR by right aligning the useful value. This allows the number of bytes transferred into the TDR to match the number set up in the BCNT field of the MCI Block Register (BLKR). 32003KS–AVR32–10/07 AT32AP7000 56 ...
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... Rewritten the Register Configuration Guide and renamed it “Register Configuration Example“ in ”LCD Controller (LCDC)” on page 800. Updated formula for pixel clock in ”LCD Control Register 1” on page AT32AP7000 ”Peripherals” on page 75“. ”Peripherals” on page 75. 80. ”HSB Bus Matrix (HMATRIX)” on page ” ...
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... KHz oscillator operation” on page Updated register names in ”Real Time Counter (RTC)” on page Updated register names in ”Watchdog Timer (WDT)” on page Updated register descriptions in ”HSB Bus Matrix (HMATRIX)” on page AT32AP7000 932 ”Peripherals” on page Table 1-9 on page 38. ...
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... Removed 150CGU from ”Ordering Information” on page Added ”USB Device - High Speed (480 Mbits/s)” on page Some occurences of AP7000 renamed to AT32AP7000. Updated ”Real Time Counter” on page Updated ”Audio DAC - (DAC)” on page 480 Updated ”DC Characteristics” on page Updated ” ...
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... Rev. C 04/06 1. 32003KS–AVR32–10/07 Initial revision. AT32AP7000 60 ...
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... Request Signal Map ..................................................................................22 7.3DMACA Handshake Interface Map .........................................................................24 7.4Clock Connections ...................................................................................................25 7.5External Interrupt Pin Mapping ................................................................................26 7.6Nexus OCD AUX port connections ..........................................................................26 7.7Peripheral Multiplexing on IO lines ..........................................................................27 7.8Peripheral overview .................................................................................................35 8 Boot Sequence ....................................................................................... 41 8.1Starting of clocks .....................................................................................................41 8.2Fetching of initial instructions ..................................................................................41 9 Ordering Information ............................................................................. 42 10 Errata ....................................................................................................... 43 10.1Rev. C ....................................................................................................................43 32003KS–AVR32–10/07 AT32AP7000 i ...
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... B ....................................................................................................................49 10.3Rev. A ....................................................................................................................49 11 Datasheet Revision History ................................................................... 57 11.1Rev. K 09/07 ..........................................................................................................57 11.2Rev. J 07/07 ..........................................................................................................58 11.3Rev. I 04/07 ...........................................................................................................58 11.4Rev. H 02/07 ..........................................................................................................58 11.5Rev. G 10/06 .........................................................................................................59 11.6Rev. F 07/06 ..........................................................................................................59 11.7Rev. E 05/06 ..........................................................................................................59 11.8Rev. D 04/06 ..........................................................................................................59 11.9Rev. C 04/06 ..........................................................................................................60 32003KS–AVR32–10/07 AT32AP7000 ii ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2007 Atmel Corporation. All rights reserved. Atmel marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...