at32ap7002 ATMEL Corporation, at32ap7002 Datasheet - Page 7

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at32ap7002

Manufacturer Part Number
at32ap7002
Description
Avr 32 32-bit Microcontroller
Manufacturer
ATMEL Corporation
Datasheet

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32054DS–AVR32–10/07
An overview of the bus system is given in
same bus use the same clock, but the clock to each module can be individually shut off by the
Power Manager. The figure identifies the number of master and slave interfaces of each module
connected to the HSB bus, and which DMA controller is connected to which peripheral.
2 Peripheral buses allowing each bus to run on different bus speeds.
HSB-HSB Bridge providing a low-speed HSB bus running at the same speed as PBA
– Round-Robin Arbitration (three modes supported: no default master, last
– Burst Breaking with Slot Cycle Limit
– One Address Decoder Provided per Master
– PB A intended to run on low clock speeds, with peripherals connected to the PDC.
– PB B intended to run on higher clock speeds, with peripherals connected to the DMACA.
– Allows PDC transfers between a low-speed PB bus and a bus matrix of higher clock speeds
master, fixed default master)
Figure 4-1 on page
13. All modules connected to the
AT32AP7002
accessed default
7

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