p89lpc930fdh NXP Semiconductors, p89lpc930fdh Datasheet - Page 28

• Manufacturer Part Number: p89lpc930fdh
• Description: 8-bit Microcontrollers With Two-clock 80c51 Core 4 Kb/8 Kb 3 V Flash With 256-byte Data Ram
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14472
Product data
8.17.2 Mode 1
8.17.3 Mode 2
8.17.4 Mode 3
8.17.5 Baud rate generator and selection
8.17.6 Framing error
10 bits are transmitted (through TxD) or received (through RxD): a start bit (logic ‘0’),
8 data bits (LSB first), and a stop bit (logic ‘1’). When data is received, the stop bit is
stored in RB8 in Special Function Register SCON. The baud rate is variable and is
determined by the Timer 1 overflow rate or the Baud Rate Generator (described in
Section 8.17.5 “Baud rate generator and
11 bits are transmitted (through TxD) or received (through RxD): start bit (logic ‘0’),
8 data bits (LSB first), a programmable 9
data is transmitted, the 9
‘1’. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When
data is received, the 9
while the stop bit is not saved. The baud rate is programmable to either
the CPU clock frequency, as determined by the SMOD1 bit in PCON.
11 bits are transmitted (through TxD) or received (through RxD): a start bit (logic ‘0’),
8 data bits (LSB first), a programmable 9
Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in
Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate
Generator (described in section
The P89LPC930/931 enhanced UART has an independent Baud Rate Generator.
The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and
BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a
similar manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for
other timing functions.
The UART can use either Timer 1 or the baud rate generator output (see
Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses OSCCLK.
Framing error is reported in the status register (SSTAT). In addition, if SMOD0
(PCON.6) is ‘1’, framing errors can be made available in SCON.7 respectively. If
SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)
are set up when SMOD0 is ‘0’.
Fig 6. Baud rate sources for UART (Modes 1, 3).
Baud Rate Generator
Timer 1 Overflow
(CCLK-based)
(PCLK-based)
Rev. 05 — 15 December 2004
th
data bit goes into RB8 in Special Function Register SCON,
th
data bit (TB8 in SCON) can be assigned the value of ‘0’ or
¸
2
Section 8.17.5 “Baud rate generator and
8-bit microcontrollers with two-clock 80C51 core
SMOD1 = 1
SMOD1 = 0
th
th
selection”).
data bit, and a stop bit (logic ‘1’). When
data bit, and a stop bit (logic ‘1’). In fact,
SBRGS = 0
SBRGS = 1
P89LPC930/931
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Baud Rate Modes 1 and 3
1
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16
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