p89lpc9171fdh NXP Semiconductors, p89lpc9171fdh Datasheet - Page 22
p89lpc9171fdh
Manufacturer Part Number
p89lpc9171fdh
Description
8-bit Microcontroller With Accelerated Two-clock 80c51 Core, 2 Kb 3 V Byte-erasable Flash With 8-bit Adc
Manufacturer
NXP Semiconductors
Datasheet
1.P89LPC9171FDH.pdf
(91 pages)
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Table 6.
* indicates SFRs that are bit addressable.
[1]
[2]
[3]
[4]
[5]
[6]
Name
WDCON
WDL
WFEED1
WFEED2
All ports are in input only (high-impedance) state after power-up.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
The RSTSRC register reflects the cause of the P89LPC9151 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on
reset value is x011 0000.
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
The only reset sources that affect these SFRs are power-on reset and watchdog reset.
Special function registers - P89LPC9151
Description
Watchdog
control register
Watchdog load
Watchdog
feed 1
Watchdog
feed 2
SFR
addr.
C1H
C2H
C3H
A7H
Bit functions and addresses
PRE2
MSB
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
LSB
Reset value
Hex
[4][6]
FF
Binary
1111 1111
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