p80c550efaa NXP Semiconductors, p80c550efaa Datasheet - Page 22

• Manufacturer Part Number: p80c550efaa
• Description: 80c51 8-bit Microcontroller Family 4k/128 Otp/rom/romless, Channel Watchdog Timer
• Manufacturer: NXP Semiconductors

1. ’0’ = Valid low for that pin, ’1’ = valid high for that pin.
2. V
3. V
*
Philips Semiconductors
EPROM CHARACTERISTICS
The 87C550 is programmed by using a modified Quick-Pulse
Programming algorithm. It differs from older methods in the value
used for V
number of the ALE/PROG pulses.
The 87C550 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an S87C550 manufactured by
Philips.
Table 4 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
lock bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 17 and 18. Figure 19 shows the
circuit configuration for normal program memory verification.
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in
Figure 17. Note that the 87C550 is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
The address of the EPROM location to be programmed is applied to
ports 2 and 3, as shown in Figure 17. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 1 and 2 specified in Table 4 are held at the ‘Program
Code Data’ levels indicated in Table 4. The ALE/PROG is pulsed
low 25 times as shown in Figure 18.
To program the encryption table, repeat the 25 pulse programming
sequence for addresses 0 through 1FH, using the ‘Pgm Encryption
Table’ levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
To program the security bits, repeat the 25 pulse programming
sequence using the ‘Pgm Security Bit’ levels. After one security bit is
Table 4. EPROM Programming Modes
NOTES:
1998 May 01
Read signature
Program code data
Verify code data
Pgm encryption table
Pgm security bit 1
Pgm security bit 2
Trademark phrase of Intel Corporation.
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
ALE/PROG receives 25 programming pulses while V
minimum of 10 s.
PP
CC
= 12.75V 0.25V.
= 5V 10% during programming and verification.
PP
MODE
(programming supply voltage) and in the width and
RST
1
1
1
1
1
1
PSEN
0
0
0
0
0
0
PP
ALE/PROG
is held at 12.75V. Each programming pulse is low for 100 s ( 10 s) and high for a
0*
0*
0*
0*
1
1
22
EA/V
programmed, further programming of the code memory and
encryption table is disabled. However, the other security bit can still
be programmed.
Note that the EA/V
maximum specified V
glitch above that voltage can cause permanent damage to the
device. The V
and overshoot.
Program Verification
If security bit 2 has not been programmed, the on-chip program
memory can be read out for program verification. The address of the
program memory locations to be read is applied to ports 2 and 3 as
shown in Figure 19. The other pins are held at the ‘Verify Code Data’
levels indicated in Table 4. The contents of the address location will
be emitted on port 0. External pull-ups are required on port 0 for this
operation.
If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P1.0 and P1.1
need to be pulled to a logic low. The values are:
(030H) = 15H indicates manufactured by Philips
(031H) = 96H indicates S87C550
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 4, and
which satisfies the timing specifications, is suitable.
V
V
V
V
1
1
PP
PP
PP
PP
PP
PP
P2.7
source should be well regulated and free of glitches
0
1
0
1
1
1
PP
PP
80C550/83C550/87C550
pin must not be allowed to go above the
level for any amount of time. Even a narrow
P2.6
0
0
0
0
1
1
P1.1
0
1
1
1
1
0
Product specification
P1.0
0
1
1
0
1
0