p87lpc778-01 NXP Semiconductors, p87lpc778-01 Datasheet - Page 30

• Manufacturer Part Number: p87lpc778-01
• Description: P87lpc778 Cmos Single-chip 8-bit 80c51 Microcontroller With 128-byte Data Ram, 8 Kb Otp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12378
Product data
8.7.6 Regarding software response time
CSTP — Writing a ‘1’ to ‘Clear SToP’ clears the STP bit. Note that if one or more of
DRDY, ARL, STR, or STP is ‘1’, the low time of SCL is stretched until the service
routine responds by clearing them.
XSTR — Writing ‘1’s to ‘Xmit repeated STaRt’ and CDR tells the I
send a repeated start condition. This should only be at a master. Note that XSTR
need not and should not be used to send an ‘initial’ (non-repeated) start; it is sent
automatically by the I
I2DAT with XDAT = 1; it sets Transmit Active and releases SDA to HIGH during the
SCL low time. After SCL goes HIGH, the I
minimum time and then drives SDA low to make the start condition.
XSTP — Writing 1s to ‘Xmit SToP’ and CDR tells the I
condition. This should only be done at a master. If there are no more messages to
initiate, the service routine should clear the MASTRQ bit in I2CFG to ‘0’ before writing
XSTP with ‘1’. Writing XSTP = 1 includes the effect of writing I2DAT with XDAT = 0; it
sets Transmit Active and drives SDA low during the SCL low time. After SCL goes
HIGH, the I
SDA to HIGH to make the stop condition.
Table 25:
Not bit addressable; Reset value: xxH
Table 26:
Because the P87LPC778 can run at 20 MHz, and because the I
optimized for high-speed operation, it is quite likely that an I
sometimes respond to DRDY (which is set at a rising edge of SCL) and write I2DAT
before SCL has gone low again. If XDAT were applied directly to SDA, this situation
would produce an I
this possibility because XDAT is applied to SDA only when SCL is low.
Conversely, a program that includes an I
to respond to DRDY. Typically, an I
during a message, with interrupts from other peripheral functions enabled. If an
interrupt occurs, it will delay the response of the I
programmer need not worry about this very much either, because the I
hardware stretches the SCL low time until the service routine responds. The only
constraint on the response is that it must not exceed the Timer I time-out.
Bit
7
6 to 0 -
Bit
Symbol (R)
Symbol (W)
Symbol
RDAT
XDAT
I2DAT - I
I2DAT - I
2
C-bus hardware waits for the suitable minimum time and then releases
RDAT
XDAT
Access
R
W
-
Rev. 01 — 31 March 2004
2
2
7
2
C-bus data register (address D9H) bit allocation
C-bus data register (address D9H) bit description
C-bus protocol violation. The programmer need not worry about
2
C-bus hardware. Writing XSTR = 1 includes the effect of writing
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-
6
Description
The most recently received data bit, captured from SDA at
every rising edge of SCL. Reading I2DAT also clears DRDY
and the Transmit Active state.
Sets the data for the next transmitted bit. Writing I2DAT also
clears DRDY and sets the Transmit Active state.
Reserved for future use. Should not be set to ‘1’ by user
programs.
-
-
2
C-bus routine operates on a flag-polling basis
5
2
C-bus service routine may take a long time
2
-
-
C-bus hardware waits for the suitable
CMOS single-chip 8-bit microcontroller
4
2
C-bus service routine. The
-
-
2
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
3
C-bus hardware to send a stop
2
C-bus service routine will
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-
P87LPC778
2
2
C-bus interface is
2
C-bus hardware to
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2
1
C-bus
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