p87c453ebaa NXP Semiconductors, p87c453ebaa Datasheet - Page 15

• Manufacturer Part Number: p87c453ebaa
• Description: 80c51 8-bit Microcontroller Family 8k/256 Otp/rom, Expanded I/o
• Manufacturer: NXP Semiconductors

Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS
T
1998 Apr 23
amb
Data Memory
Shift Register
Port 6 input (input rise and fall times = 5ns)
SYMBOL
80C51 8-bit microcontroller family
8K/256 OTP/ROM, expanded I/O
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LHLL
AVLL
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
WHQX
RLAZ
WHLH
XLXL
QVXH
XHQX
XHDX
XHDV
FLFH
ILIH
DVIH
IHDZ
IVFV
= 0 C to +70 C, V
CLCL
FIGURE
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
12
12
12
12
12
15
15
15
15
16
9
9
9
9
9
9
9
9
9
9
9
CC
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
RD low to address float
RD or WR high to ALE high
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
PE width
IDS width
Data setup to IDS high or PE high
Data hold after IDS high or PE high
IDS to BFLAG (IBF) delay
= 5V 10%, V
SS
PARAMETER
= 0V
15
MIN
16MHz CLOCK
142
275
275
137
122
750
492
209
209
85
22
32
32
13
13
23
30
0
0
8
0
0
MAX
150
207
147
350
397
239
103
492
130
82
37
10
65
0
10t
6t
6t
4t
2t
3t
3t
2t
3t
3t
t
t
t
t
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
12t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
MIN
3.5
30
VARIABLE CLOCK
CLCL
0
0
0
0
–40
–30
–30
–100
–100
–130
–50
–50
–40
–117
–40
–45
–50
–133
+20
+20
83C453/87C453
10t
4t
3t
5t
5t
8t
9t
2t
3t
t
t
Preliminary specification
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
MAX
130
16
10
0
+40
–100
–105
–25
–105
–165
–150
–165
–60
+50
–133
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns