p87c453ebaa NXP Semiconductors, p87c453ebaa Datasheet - Page 9

• Manufacturer Part Number: p87c453ebaa
• Description: 80c51 8-bit Microcontroller Family 8k/256 Otp/rom, Expanded I/o
• Manufacturer: NXP Semiconductors

Philips Semiconductors
1998 Apr 23
NOTE:
*SMOD0 is located at PCON6.
**f
80C51 8-bit microcontroller family
8K/256 OTP/ROM, expanded I/O
OSC
Symbol
FE
SM0
SM1
SM2
REN
TB8
RB8
Tl
Rl
= oscillator frequency
Bit Addressable
Bit:
Function
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
0
0
1
1
SCON Address = 98H
(SMOD0 = 0/1)*
SM0/FE
7
SM1
START
0
1
0
1
BIT
SM0 / FE
SMOD1
SM1
Mode
6
D0
0
1
2
3
0 : SCON.7 = SM0
1 : SCON.7 = FE
SMOD0
SM1
Figure 5. Serial Port Control Register (SCON)
D1
SM2
Figure 6. UART Framing Error Detection
5
Description
shift register
8-bit UART
9-bit UART
9-bit UART
SM2
D2
–
REN
4
REN
D3
POF
DATA BYTE
Baud Rate**
f
variable
f
variable
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)
SM0 TO UART MODE CONTROL
OSC
OSC
TB8
9
/12
/64 or f
3
TB8
D4
LVF
OSC
RB8
D5
/32
2
RB8
GF0
D6
GF1
TI
Tl
1
D7
IDL
RI
MODE 2, 3
Rl
ONLY IN
0
D8
SCON
(98H)
PCON
(87H)
Reset Value = 0000 0000B
83C453/87C453
STOP
BIT
Preliminary specification
SU00044
SU00043