lpc2103fa44 NXP Semiconductors, lpc2103fa44 Datasheet - Page 18

• Manufacturer Part Number: lpc2103fa44
• Description: Single-chip 16-bit/32-bit Microcontrollers; 8 Kb/16 Kb/32 Kb Flash With Isp/iap, Fast Ports And 10-bit Adc
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2101_02_03_2
Preliminary data sheet
6.17.3 Reset and wake-up timer
6.17.4 Code security
6.17.5 External interrupt inputs
6.17.6 Memory mapping control
Reset has two sources on the LPC2101/2102/2103: the RST pin and watchdog reset. The
RST pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset
by any source starts the wake-up timer (see wake-up timer description below), causing
the internal chip reset to remain asserted until the external reset is de-asserted, the
oscillator is running, a fixed number of clocks have passed, and the on-chip flash
controller has completed its initialization.
When the internal reset is removed, the processor begins executing at address 0, which is
the reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined reset values.
The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This
is important at power on, all types of reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the wake-up timer.
The wake-up timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
This feature of the LPC2101/2102/2103 allow an application to control whether it can be
debugged or protected from observation.
If after reset on-chip bootloader detects a valid checksum in flash and reads 0x8765 4321
from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be
protected from observation. Once debugging is disabled, it can only be enabled by
performing a full chip erase using the ISP.
The LPC2101/2102/2103 include up to three edge or level sensitive external interrupt
inputs as selectable pin functions. When the pins are combined, external events can be
processed as three independent interrupt signals. The external interrupt inputs can
optionally be used to wake-up the processor from Power-down mode.
Additionally all 10 capture input pins can also be used as external interrupts without the
option to wake the device up from Power-down mode.
The memory mapping control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
Rev. 02 — 18 December 2007
DD
ramp (in the case of power on), the type of crystal
Single-chip 16-bit/32-bit microcontrollers
LPC2101/2102/2103
© NXP B.V. 2007. All rights reserved.
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