lpc2103fa44 NXP Semiconductors, lpc2103fa44 Datasheet - Page 8

• Manufacturer Part Number: lpc2103fa44
• Description: Single-chip 16-bit/32-bit Microcontrollers; 8 Kb/16 Kb/32 Kb Flash With Isp/iap, Fast Ports And 10-bit Adc
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 3.
LPC2101_02_03_2
Preliminary data sheet
Symbol
P0.21/SSEL1/
MAT3.0
P0.22/AD0.0
P0.23/AD0.1
P0.24/AD0.2
P0.25/AD0.6
P0.26/AD0.7
P0.27/TRST/
CAP2.0
P0.28/TMS/
CAP2.1
P0.29/TCK/
CAP2.2
P0.30/TDI/
MAT3.3
P0.31/TDO
RTCX1
RTCX2
RTCK
XTAL1
XTAL2
DBGSEL
Pin description
LQFP48
3
32
33
34
38
39
8
9
10
15
16
20
25
26
11
12
27
[4]
[4]
[4]
[4]
[1]
[1]
[1]
[1]
[4]
[4]
[4]
[5]
[5]
[5]
…continued
PLCC44
9
35
36
37
41
n.c.
13
14
15
20
21
24
29
n.c.
16
17
30
[4]
[4]
[1]
[1]
[1]
[4]
[4]
[4]
[4]
[4]
[5]
[5]
Rev. 02 — 18 December 2007
Type
I/O
I
O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I
I/O
I
I
I/O
I
I
I/O
I
O
O
O
I
O
I/O
I
O
I
Description
P0.21 — General purpose input/output digital pin.
SSEL1 — Slave Select for SPI1. Selects the SPI interface as
a slave.
MAT3.0 — PWM output for Timer 3, channel 0.
P0.22 — General purpose input/output digital pin.
AD0.0 — ADC 0, input 0.
P0.23 — General purpose input/output digital pin.
AD0.1 — ADC 0, input 1.
P0.24 — General purpose input/output digital pin.
AD0.2 — ADC 0, input 2.
P0.25 — General purpose input/output digital pin.
AD0.6 — ADC 0, input 6.
P0.26 — General purpose input/output digital pin.
AD0.7 — ADC 0, input 7.
P0.27 — General purpose input/output digital pin.
TRST — Test Reset for JTAG interface.
CAP2.0 — Capture input for Timer 2, channel 0.
P0.28 — General purpose input/output digital pin.
TMS — Test Mode Select for JTAG interface.
CAP2.1 — Capture input for Timer 2, channel 1.
P0.29 — General purpose input/output digital pin.
TCK — Test Clock for JTAG interface. This clock must be
slower than
to operate.
CAP2.2 — Capture input for Timer 2, channel 2.
P0.30 — General purpose input/output digital pin.
TDI — Test Data In for JTAG interface.
MAT3.3 — PWM output 3 for Timer 3.
P0.31 — General purpose output only digital pin.
TDO — Test Data Out for JTAG interface.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
Returned test clock output: Extra signal added to the JTAG
port. Assists debugger synchronization when processor
frequency varies. Bidirectional pin with internal pull-up.
Input to the oscillator circuit and internal clock generator
circuits.
Output from the oscillator amplifier.
Debug select: When LOW, the part operates normally. When
HIGH, debug mode is entered. Input with internal pull-down.
1
6
Single-chip 16-bit/32-bit microcontrollers
of the CPU clock (CCLK) for the JTAG interface
LPC2101/2102/2103
© NXP B.V. 2007. All rights reserved.
8 of 32