lpc2364 NXP Semiconductors, lpc2364 Datasheet - Page 31

• Manufacturer Part Number: lpc2364
• Description: Single-chip 16-bit/32-bit Microcontrollers; Up To 512 Kb Flash With Isp/iap, Ethernet, Usb 2.0, Can, And 10-bit Adc/dac
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2364_66_68_3
Product data sheet
7.24.4.3 Power-down mode
7.24.4.4 Power domains
7.25.1 Reset
7.25 System control
On the wake-up of Sleep mode, if the IRC was used before entering Sleep mode, the code
execution and peripherals activities will resume after 4 cycles expire. If the main external
oscillator was used, the code execution will resume when 4096 cycles expire.
The customers need to reconfigure the PLL and clock dividers accordingly.
Power-down mode does everything that Sleep mode does, but also turns off the IRC
oscillator and the flash memory. This saves more power, but requires waiting for
resumption of flash operation before execution of code or data access in the flash memory
can be accomplished.
On the wake-up of Power-down mode, if the IRC was used before entering Power-down
mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code
execution can then be resumed if the code was running from SRAM. In the meantime, the
flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 s flash start-up
time. When it times out, access to the flash will be allowed. The customers need to
reconfigure the PLL and clock dividers accordingly.
The LPC2364/66/68 provides two independent power domains that allow the bulk of the
device to have power removed while maintaining operation of the RTC and the Battery
RAM.
The 3.3 V (V
These pins provide the power for the CPU and most of the peripherals. If power is
removed from the V
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
Reset has four sources on the LPC2364/66/68: the RESET pin, the Watchdog reset,
power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains
a usable level, starts the Wake-up timer (see description in
timer”), causing reset to remain asserted until the external Reset is de-asserted, the
oscillator is running, a fixed number of clocks have passed, and the flash controller has
completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
DD(3V3)
) pins power both the on-chip DC-to-DC converter and the I/O pads.
DD(3V3)
Rev. 03 — 20 December 2007
pins, the CPU and related peripherals stop.
LPC2364/66/68
Section 7.24.3 “Wake-up
Fast communication chip
© NXP B.V. 2007. All rights reserved.
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