p89c538nbb NXP Semiconductors, p89c538nbb Datasheet - Page 22

• Manufacturer Part Number: p89c538nbb
• Description: Cmos Single-chip 8-bit Microcontrollers With Flash Program Memory
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FLASH EPROM PROGRAM MEMORY
FEATURES
GENERAL DESCRIPTION
The 89C536/538 FLASH EPROM memory augments EPROM
functionality with In–circuit electrical erasure and programming. The
89C536/538 uses a command register to manage this functionality.
The FLASH EPROM reliably stores memory contents even after 100
erase and program cycles. The cell is designed to optimize the
erase and programming mechanisms. In addition, the combination
of advanced tunnel oxide processing and low internal electric fields
for erase and programming operations produces reliable cycling.
The 89C536/538 uses a 12.0V "5%V
Program/Erase algorithms.
Automatic Programming
The 89C536/538 is byte programmable using the Automatic
Programming algorithm. The Automatic Programming algorithm
does not require the system to time out or verify the data
programmed. The typical room temperature chip programming time
of the 89C536/538 is less than 5 seconds.
1998 Apr 24
16K (89C536) or 64K (89C538) or electrically erasable internal
program.
Up to 64 Kilobyte external program memory if the internal program
memory is switched off (EA = 0).
Programming and erasing voltage 12V "5%
Command register architecture
– Byte Programming (10 s typical)
– Auto chip erase 5 seconds typical (including preprogramming
Auto Erase and auto program
– DATA polling
– Toggle bit
100 minimum erase/program cycles
Advanced CMOS FLASH EPROM memory technology
80C51 8-bit microcontroller family
16K/64K/512 FLASH
time)
4–6 MHz
A0–A7
CE
1
PP
supply to perform the Auto
Figure 21.
P1
RST
P3.3
XTAL2
XTAL1
VSS
Erase/Programming/Verification
89C536/538
P2.6, P3.7, P3.1, P3.0
22
P2.0–P2.5
Automatic Chip Erase
The device may be erased using the automatic Erase algorithm. The
automatic Erase algorithm automatically programs the entire array
prior to electrical erase. The timing and verification of electrical
erase are controlled internal to the device.
Automatic Programming Algorithm
The 89C536/538 automatic Programming algorithm requires the
user to only write a program set–up command and a program
command (program data and address). The device automatically
times the programming pulse width, provides the program verify, and
counts the number of sequences. A status bit similar to DATA
polling and a status bit toggling between consecutive read cycles,
provide feedback to the user as to the status of the programming
operation.
AUTOMATIC ERASE ALGORITHM
The 89C536/538 Automatic Erase algorithm requires the user to
only write an erase set–up command and erase command. The
device will automatically pre–program and verify the entire array.
Then the device automatically times the erase pulse width, provides
the erase verify, and counts the number of sequences. A status bit
similar to DATA polling and a status bit toggling between
consecutive read cycles, provide feedback to the user as to the
status of the erase operation.
Commands are written to the command register. Register contents
serve as inputs to an internal state–machine which controls the
erase and programming circuitry. During write cycles, the command
register internally latches address and data needed for the
programming and erase operations. For system design
simplification, the 89C536/538 is designed to support either WE or
CE controlled writes. During a system write cycle, addresses are
latched on the falling edge of WE or CE, whichever occurs last. Data
is latched on the rising edge of WE or CE, whichever occurs first. To
simplify the following discussion, the WE pin is used as the write
cycle control pin through the rest of this text. All setup and hold
times are with respect to the WE signal.
ALE/WE
PSEN
VDD
P2.7
P3.5
P3.4
EA
P0
+5V
PGM COMMAND/DATA
V
LOW PULSE
0
OE
A15
A8–A13
A14
0000b
PP
89C536/89C538
SU00876
Preliminary specification