p89c538nbbb NXP Semiconductors, p89c538nbbb Datasheet - Page 13

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p89c538nbbb

Manufacturer Part Number
p89c538nbbb
Description
Cmos Single-chip 8-bit Microcontrollers With Flash Program Memory
Manufacturer
NXP Semiconductors
Datasheet
1. L = Level activated
2. T = Transition activated
Philips Semiconductors
Interrupt Priority Structure
The 89C535/536/538 has a 6-source two-level interrupt structure
(see Table 7). There are 2 SFRs associated with the interrupts on
the 89C535/536/538. They are the IE and IP. (See Figures 6 and 7.)
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
Table 7.
NOTES:
1997 Jun 05
PRIORITY BITS
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
IP.x
0
1
SOURCE
SP
X0
T0
X1
T1
T2
Interrupt Table
Level 0 (lowest priority)
Level 1 (highest priority)
INTERRUPT PRIORITY LEVEL
INTERRUPT PRIORITY LEVEL
POLLING PRIORITY
1
2
3
4
5
6
REQUEST BITS
TF2, EXF2
R1, TI
TP0
TF1
IE0
IE1
13
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
HARDWARE CLEAR?
N (L)
N (L) Y (T)
89C535/89C536/89C538
1
Y
Y
N
N
Y (T)
2
VECTOR ADDRESS
Preliminary specification
0BH
1BH
2BH
03H
13H
23H

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