p89cv51rb2 NXP Semiconductors, p89cv51rb2 Datasheet
p89cv51rb2
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p89cv51rb2 Summary of contents
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... RAM, SPI, 6-clock CPU with 6/12-clock peripherals Rev. 01 — 5 October 2007 1. General description The P89CV51RB2/RC2/RD2 are three types of 80C51 microcontroller with respectively 16 kB/32 kB/64 kB flash and data RAM. These devices are designed to be drop-in and software-compatible replacements for the popular P89C51RB2/RC2/RD2 devices. ...
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... I Idle mode 2.3 Comparison to P89C51RB2/RC2/RD2 devices I SPI: The P89CV51RB2/RC2/RD2 devices have an SPI interface that was not present on the P89C51RB2/RC2/RD2 devices. I Smaller block size: The page size decreased from 128 B. These smaller pages can be erased and reprogrammed using IAP function calls, which makes practical use of code memory for non-volatile data storage ...
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... NXP Semiconductors 4. Block diagram P89CV51RB2/RC2/RD2 P3[7:0] P2[7:0] P1[7:0] P0[7:0] XTAL1 CRYSTAL OR RESONATOR XTAL2 Fig 1. Block diagram P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 HIGH PERFORMANCE 80C51 CPU 16 kB/32 kB/64 kB CODE FLASH internal bus 1 kB DATA RAM PORT 3 PORT 2 PORT 1 PORT 0 OSCILLATOR Rev. 01 — 5 October 2007 80C51 with 1 kB RAM, SPI ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. PLCC44 pin configuration P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 P1[5]/CEX2/MOSI 7 P1[6]/CEX3/MISO 8 9 P1[7]/CEX4/SPICLK 10 RST P3[0]/RXD 11 P89CV51RB2/RC2/RD2 n. P3[1]/TXD P3[2]/INT0 14 P3[3]/INT1 15 16 P3[4]/T0 17 P3[5]/T1 Rev. 01 — 5 October 2007 80C51 with 1 kB RAM, SPI 39 P0[4]/AD4 38 P0[5]/AD5 37 P0[6]/AD6 36 P0[7]/AD7 ...
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... NXP Semiconductors Fig 3. TQFP44 pin configuration 5.2 Pin description Table 3. P89CV51RB2/RC2/RD2 Pin description Symbol Pin PLCC44 TQFP44 P0[0] to P0[7] P0[0]/AD0 43 37 P0[1]/AD1 42 36 P0[2]/AD2 41 35 P0[3]/AD3 40 34 P0[4]/AD4 39 33 P0[5]/AD5 38 32 P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 P1[5]/CEX2/MOSI 1 P1[6]/CEX3/MISO 2 3 P1[7]/CEX4/SPICLK RST 4 P3[0]/RXD 5 P89CV51RB2/RC2/RD2 n ...
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... NXP Semiconductors Table 3. P89CV51RB2/RC2/RD2 Pin description Symbol Pin PLCC44 TQFP44 P0[6]/AD6 37 31 P0[7]/AD7 36 30 P1[0] to P1[7] P1[0]/ P1[1]/T2EX 3 41 P1[2]/ECI 4 42 P1[3]/CEX0 5 43 P1[4]/CEX1 P1[5]/CEX2 MOSI P1[6]/CEX3 MISO P1[7]/CEX4 SPICLK P2[0] to P2[7] P2[0]/ P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 …continued Type Description I/O P0[6] — ...
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... NXP Semiconductors Table 3. P89CV51RB2/RC2/RD2 Pin description Symbol Pin PLCC44 TQFP44 P2[1]/ P2[2]/A10 26 20 P2[3]/A11 27 21 P2[4]/A12 28 22 P2[5]/A13 29 23 P2[6]/A14 30 24 P2[7]/A15 31 25 P3[0] to P3[7] P3[0]/RXD 11 5 P3[1]/TXD 13 7 P3[2]/INT0 14 8 P3[3]/INT1 15 9 P3[4]/ P3[5]/ P3[6]/ P3[7]/ PSEN 32 26 P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 … ...
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... NXP Semiconductors Table 3. P89CV51RB2/RC2/RD2 Pin description Symbol Pin PLCC44 TQFP44 RST ALE 33 27 XTAL1 21 15 XTAL2 [1] ALE loading issue: When ALE pin experiences higher loading (> 30 pF) during the reset, the microcontroller may accidentally enter into modes other than normal working mode ...
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Table 4. Special function registers * indicates SFRs that are bit addressable. Name Description SFR address Bit address ACC* Accumulator AUXR Auxiliary function Register AUXR1 Auxiliary function Register 1 Bit address B* B register CCAP0H Module 0 Capture High CCAP1H ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR address DPTR Data Pointer (2 B) DPH Data Pointer High DPL Data Pointer Low Bit address IE* Interrupt Enable Bit address IP* Interrupt Priority ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR address Bit address SPCR SPI Control Register SPSR SPI Status Register SPDAT SPI Data SP Stack Pointer Bit address TCON* Timer/counter Control Bit address ...
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... P89CV51RB2/RC2/RD2 have 768 B of on-chip XDATA memory. • CODE code memory space, accessed as part of program execution and via the MOVC instruction. The P89CV51RB2/RC2/RD2 have 16/32/ on-chip code memory. 6.2.1 Expanded data RAM addressing The P89CV51RB2/RC2/RD2 have data RAM; see To access the expanded RAM (XRAM), the EXTRAM bit must be set and MOVX instructions must be used. The extra memory is physically located on the chip and logically occupies the fi ...
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... B and upper 128 B). The stack pointer may not be located in any part of the expanded RAM. Table 7. AUXR EXTRAM = 0 EXTRAM = 1 P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 AUXR - Auxiliary function register (address 8EH) bit description Symbol Description - Reserved for future use. Should be set user programs. EXTRAM Internal/external RAM access using MOVX @Ri/@DPTR. When 1, accesses internal XRAM with address specifi ...
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... FFH EXPANDED RAM 768 B 80H 7FH (INDIRECT ADDRESSING) 00H 000H FFFFH 0300H EXPANDED RAM Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI FFH (DIRECT (INDIRECT ADDRESSING) ADDRESSING) SPECIAL FUNCTION UPPER 128 B REGISTERS (SFRs) 80H INTERNAL RAM LOWER 128 B INTERNAL RAM ...
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... MCU will start executing code from the boot address. The boot address is formed using the value of the boot vector as the high byte of the address and 00H as the low byte. P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 AUXR1 / bit0 DPS DPS = 0 DPTR0 ...
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... Fig 6. Power-on reset circuit 6.3 Flash memory 6.3.1 Flash organization The P89CV51RB2/RC2/RD2 program memory consists of a 16/32/64 kB block for user code. The flash can be read or written in bytes and can be erased in 128-B pages. A chip erase function will erase the entire user code memory and its associated security bits. ...
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... Power-on reset code execution The P89CV51RB2/RC2/RD2 contains two special flash elements: the boot vector and the boot status bit. Following reset, the P89CV51RB2/RC2/RD2 examines the contents of the boot status bit. If the boot status bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’ ...
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... This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the P89CV51RB2/RC2/RD2 to establish the baud rate. The ISP firmware provides auto-echo of received characters. Once baud rate initialization has been performed, the ISP fi ...
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... NXP Semiconductors Table 11. Record type 03 P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 ISP Hex record formats …continued Command/data function Miscellaneous write functions :nnxxxx03ffssddcc Where number of bytes in the record xxxx = required field but value is a don’t care ff = subfunction code ss = selection code dd = data (if needed) ...
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... NXP Semiconductors Table 11. Record type 03 (continued) Subfunction code = 01 (erase blocks) P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 ISP Hex record formats …continued Command/data function block code, as shown below block kB, 00H block kB, 20H block kB, 40H ...
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... NXP Semiconductors Table 11. Record type P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 ISP Hex record formats …continued Command/data function Display device data or blank check :05xxxx04sssseeeeffcc Where 05 = number of bytes in the record xxxx = required field but value is a don’t care 04 = function code for display or blank check ssss = starting address, MSB fi ...
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... PGM_MTP at FFF0H. The IAP calls are shown in Table 12. IAP function Read ID Erase 4 kB code block (new function) P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 IAP function calls IAP call parameters Input parameters 00H or 80H (WDT feed) DPH = 00H DPL = 00H = manufacturer ID DPL = 01H = device ID 1 ...
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... Erase 8 kB/16 kB code block Program user code Read user code Erase status bit and boot vector Program security bits P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 IAP function calls …continued IAP call parameters Input parameters 01H or 81H (WDT feed) DPH = 00H, block ...
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... In addition to the ‘Timer’ or ‘Counter’ selection, Timer 0 and Timer 1 have four selectable operating modes. P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 IAP function calls …continued IAP call parameters Input parameters: ...
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... Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits (Timer 1) timer/counter 1 stopped. TCON - Timer/Counter control register (address 88H) bit allocation TF1 TR1 TF0 Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI T1M0 T0GATE T0C TR0 IE1 ...
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... Cleared by hardware when the interrupt is processed software. IT0 Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/LOW-state that triggers external interrupt 0. Figure TRn Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI shows Mode 0 operation. overflow TLn THn (5-bits) (8-bits) control (Table 17) ...
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... Timer 1 interrupt. Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in mode 3, the P89CV51RB2/RC2/RD2 can look like it has an additional timer. Note: When Timer Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator any application not requiring an interrupt ...
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... Receive clock flag. When set, causes the UART to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overfl used for the receive clock. Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI overflow TL0 ...
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... Reserved for future use. Should be set user programs. T2OE Timer 2 Output Enable bit. Used in programmable Clock-out mode only. DCEN Down Count Enable bit. When set, this allows Timer configured as an up/down counter. Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI / ...
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... When reset is applied, DCEN = 0 and Timer 2 will default to shows Timer 2 counting up automatically (DCEN = 0). C/ TL2 (8-bits) control C/ TR2 reload RCAP2L RCAP2H control EXEN2 Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI TH2 TF2 (8-bits) EXF2 / 6 pulses. Since once osc TH2 TF2 (8-bits) EXF2 timer 2 ...
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... DCEN = 1 and Timer 2 is enabled to count up or down. This mode allows pin (down-counting reload value) FFH TL2 (8-bits) control TR2 RCAP2L RCAP2H (up-counting reload value) Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI toggle FFH underflow TH2 TF2 (8-bits) overflow count direction ...
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... With these two bits, the serial port can have different receive and transmit baud rates – Timer 1 or Timer 2. Figure 14 OSC T2 pin Fig 14. Timer 2 in Baud rate generator mode P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 – RCAP2H RCAP2L shows Timer 2 in Baud rate generator mode TR2 ...
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... Equation OscillatorFrequency – RCAP2H RCAP2L / (16 (65536 (RCAP2H, RCAP2L))) osc = oscillator frequency osc f / (16 osc Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI 1 the oscillator 6 3: Table 23 shows commonly used baud baud rate) (3) © NXP B.V. 2007. All rights reserved ...
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... In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in mode 3 is variable and is determined by the Timer 1/Timer 2 overflow rate. P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 Timer 2-generated commonly used baud rates Oscillator frequency 12 MHz 12 MHz ...
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... Framing Error (FE) is reported in the SCON.7 bit if SMOD0 (PCON. SMOD0 = 0, SCON.7 is the SM0 bit for the UART recommended that SM0 is set up before SMOD0 is set to 1. P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 SCON - Serial port control register (address 98H) bit allocation ...
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... The slaves that were not addressed leave their SM2 bits set and ignore the subsequent data bytes. P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 Rev. 01 — 5 October 2007 80C51 with 1 kB RAM, SPI © NXP B.V. 2007. All rights reserved. ...
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... UART to detect 'given address' in received data multiprocessor communications is enabled Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI Figure 15 to determine if a given or broadcast given_address_match broadcast_address_match 002aaa527 © NXP B.V. 2007. All rights reserved ...
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... This effectively disables the automatic addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature. P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 Rev. 01 — 5 October 2007 80C51 with 1 kB RAM, SPI © NXP B.V. 2007. All rights reserved ...
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... Wake-up from Idle mode (Slave mode only) 6.7.2 SPI description The serial peripheral interface allows high-speed synchronous data transfer between the P89CV51RB2/RC2/RD2 and peripheral devices or between several P89CV51RB2/RC2/RD2 devices. and slave SPI devices. The SPICLK pin is the clock output and input for the Master and Slave modes, respectively ...
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... WCOL Write Collision flag. Set if the SPI data register is written to during data transfer. This bit is cleared by software. - Reserved for future use. Should be set user programs. Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI MSTR CPOL ...
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... MISO MSB 6 (from slave) SS (to slave) SCK cycle # 1 2 (for reference) MOSI MSB 6 (from master) MISO MSB 6 (from slave) SS (to slave) Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI LSB LSB ...
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... PCA TIMER/COUNTER Module functions: - 16-bit capture - 16-bit timer - 16-bit high speed output - 8-bit PWM - watchdog timer (module 4 only) Figure 20. Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI 1 the oscillator frequency bits MODULE0 MODULE1 MODULE2 MODULE3 MODULE4 Figure 20 ...
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... MODULE1 MODULE2 MODULE3 MODULE4 CMOD.0 ECF Fig 20. PCA interrupt system Table 32. Not bit addressable; reset value: 00H. Bit Symbol P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 CCAPMn.0 ECCFn CMOD - PCA counter mode register (address C1H) bit allocation CIDL WDTE - Rev. 01 — 5 October 2007 ...
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... P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 CMOD - PCA counter mode register (address C1H) bit description Symbol Description CIDL Counter Idle control. CIDL = 0 programs the PCA counter to continue functioning during Idle mode; CIDL = 1 programs gated off during Idle mode. ...
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... X 0 Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI CAPNn MATn TOGn ECCFn Module function 0 no operation X 16-bit capture by a positive-edge trigger on CEXn X 16-bit capture by a negative-edge trigger on CEXn X 16-bit capture by any transition on CEXn ...
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... MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set. P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 - CCF4 CCF3 CCF2 ...
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... COMPARATOR CH CL PCA timer/counter - ECOMn CAPPn CAPNn 0 0 (Figure 23) the CEX output (on port 1) associated with the PCA module will Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI CCF3 CCF2 CCF1 CCF0 (to CCFn) MATn TOGn PWMn ECCFn ...
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... PCA timer/counter - ECOMn CAPPn CAPNn 0 0 CCAPnH CCAPnL 8-BIT COMPARATOR CL PCA timer/counter CAPNn MATn TOGn Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI CCF3 CCF2 CCF1 CCF0 (to CCFn) MATn TOGn PWMn ECCFn (Figure 24). Output frequency 0 CL CCAPnL CL ...
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... CCAP4L,#00 ;Next compare value is within 255 counts of current PCA timer value CCAP4H,CH EA ;Re-enable interrupts Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI Figure 24 shows a diagram of how the 16 PCA timer © NXP B.V. 2007. All rights reserved ...
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... Vector address Interrupt enable 0003H EX0 000BH ET0 0013H EX1 001BH ET1 0023H ES 0023H ES 0033H EC 003BH ET2 Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI Table 40. Figure 25. Interrupt Service priority priority PX0/PX0H 1 (highest) PT0/PT0H 2 PX1/PX1H 3 PT1/PT1H 4 PS/PSH 5 ...
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... IE - Interrupt enable register 0 (address A8H) bit description Symbol Description EA Interrupt Enable interrupt(s) can be serviced interrupt servicing disabled. EC PCA interrupt Enable. ET2 Timer 2 interrupt Enable. Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI registers ET1 EX1 highest priority ...
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... Table 47. Bit P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 IE - Interrupt enable register 0 (address A8H) bit description Symbol Description ES Serial port interrupt Enable. ET1 Timer 1 overflow interrupt Enable. EX1 External interrupt 1 Enable. ET0 Timer 0 overflow interrupt Enable. EX0 External interrupt 0 Enable ...
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... PCON) MOV PCON, #01H Power-down Software (Set PD bit in PCON) MOV PCON, #02H P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 level is 4 line is restored to its normal operating voltage. Be sure to hold V DD State of MCU CLK is running. Interrupts, serial port and timers/counters are active. Program counter is stopped ...
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... Table 49 shows the typical values for C Recommended values for C and n.c. external oscillator signal Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI and V specifications and C should be adjusted appropriately for 1 2 and C versus resonator type for ...
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... Table 52. FX2 clock mode bit X2 bit erased programmed P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 CKCON - Clock control register (address 8FH) bit allocation SPIX2 WDX2 PCAX2 CKCON - Clock control register (address 8FH) bit description Symbol Description SPIX2 SPI clock clock cycles for each SPI clock cycle; ...
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... LOW-level output voltage OL V HIGH-level output voltage OH I LOW-level input current IL I HIGH-LOW transition THL current I input leakage current LI P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 unless otherwise noted. SS Conditions on EA pin except V ; with respect transfer, not device power consumption = Conditions [1] ...
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... OL may exceed the related specification. Pins are not guaranteed to sink current greater than the OH on ALE and PSEN to momentarily fall below the V OH Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI Min Typ Max 40 - ...
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... Maximum active I DD (2) Maximum idle I DD (3) Typical active I DD (4) Typical idle I DD Fig 28 function of frequency DD P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 10 20 Rev. 01 — 5 October 2007 80C51 with 1 kB RAM, SPI 002aaa813 (1) (2) (3) ( internal clock frequency (MHz) © NXP B.V. 2007. All rights reserved. ...
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... QVWH t RD LOW to address float time RLAZ HIGH to ALE HIGH time WHLH [ cy(clk) osc [2] Calculated values are for 6-clock mode only. P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 [1][ Conditions Min 12-clock mode 0 6-clock mode 0 IAP 0.25 2T cy(clk) T cy(clk) T cy(clk) ...
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... LLIV t LLPL t PLIV t PLAZ t LLAX INSTR IN t AVIV A8 to A15 Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI Figure 33 has 5 characters. The first character is t PLPH t PXAV t PXIZ t PXIX A15 002aaa548 © NXP B.V. 2007. All rights reserved. ...
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... P2 A15 from DPH t t WLWH LLWL t LLAX t QVWH DATA OUT t AVWL P2[7: A15 from DPH Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI t WHLH t RHDZ from PCL A0 to A15 from PCH t WHLH t WHQX from PCL INSTR IN ...
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... CHCL CLCX Oscillator 40 MHz Min Max 0.3 - 117 - 117 Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI Variable Min Max 0.35T 0.65T cy(clk) 0.35T 0.65T cy(clk CHCX t CLCH T cy(clk) 002aaa907 Variable Min Max ...
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... SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) see Figure 34, 35, 36, 37 SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI valid valid valid valid Variable clock f osc Min ...
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... MOSI SPIF (output) Fig 34. SPI master timing (CPHA = 0) SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t SPIF MOSI (output) Fig 35. SPI master timing (CPHA = 1) P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 T SPICYC t t SPIF t SPICLKL t SPICLKH t t SPIF SPIR t SPICLKL t SPICLKH t t SPIDSU ...
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... SPIR t SPICLKL t SPICLKH t SPIR t SPICLKL t SPICLKH t SPIOH t SPIDV slave MSB/LSB out t t SPIDSU SPIDH MSB/LSB in Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI t t SPILAG t SPIOH slave LSB/MSB out not defined t t SPIDSU SPIDH LSB/MSB in 002aaa910 t SPIR t SPILAG t SPIOH t ...
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... DUT V DD (n.c.) clock signal All other pins disconnected test condition, Active mode DD (n.c.) clock signal All other pins disconnected test condition, Idle mode DD Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI to tester C L 002aaa555 RST ...
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... NXP Semiconductors Fig 41. I P89CV51RB2_RC2_RD2_1 Product data sheet V DD RST (n.c.) XTAL2 XTAL1 V SS All other pins disconnected test condition, Power-down mode DD Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI = 4 DUT 002aad019 © NXP B.V. 2007. All rights reserved. ...
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... 2.5 scale (1) ( 0.45 0.18 10.1 10.1 12.15 12.15 0.8 0.30 0.12 9.9 9.9 11.85 11.85 REFERENCES JEDEC JEITA MS-026 Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI detail 0.75 1.2 1 0.2 0.2 0.1 0.45 0.8 EUROPEAN PROJECTION SOT376 (1) ...
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... 0.81 16.66 16.66 16.00 16.00 17.65 1.27 0.66 16.51 16.51 14.99 14.99 17.40 0.032 0.656 0.656 0.63 0.63 0.695 0.05 0.026 0.650 0.650 0.59 0.59 0.685 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 01 — 5 October 2007 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI detail 17.65 1.22 1.44 0.18 0.18 0.1 17.40 1.07 1.02 0.695 ...
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... PCH PCL PWM RAM RC SFR SPI SRAM UART WDT P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 Abbreviations Description Address Latch Enable Central Processing Unit Data PoinTeR Device Under Test Erasable Programmable Read-Only Memory Electro-Magnetic Interference IDentifier In-Application Programming In-System Programming Least Significant Bit MicroController Unit Most Signifi ...
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... NXP Semiconductors 12. Revision history Table 60. Revision history Document ID Release date P89CV51RB2_RC2_RD2_1 20071005 P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 Data sheet status Change notice Supersedes Product data sheet - Rev. 01 — 5 October 2007 80C51 with 1 kB RAM, SPI - © NXP B.V. 2007. All rights reserved. ...
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... Contact information For additional information, please visit: For sales office addresses, send an email to: P89CV51RB2_RC2_RD2_1 Product data sheet P89CV51RB2/RC2/RD2 [3] Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: P89CV51RB2_RC2_RD2_1 All rights reserved. Date of release: 5 October 2007 ...