lh79524 NXP Semiconductors, lh79524 Datasheet - Page 16

• Manufacturer Part Number: lh79524
• Description: Lh79524; Lh79525 System-on-chip
• Manufacturer: NXP Semiconductors

LH79524/LH79525
3, 26, 33,
129, 135,
5, 27, 49,
132, 140,
16
107, 150
NO.
PIN NO.
144, 160
152, 168
PIN
105,148
86, 101,
92, 108,
57, 75,
68, 81,
1
6, 66,
7, 64,
163
176
175
174
173
172
127
128
125
126
122
123
121
124
24
22
23
50
51
46
45
47
48
10
21
4
2
1
8
9
FUNCTION
AT RESET
Table 6. LH79525 Numerical Pin List
PI2
PH7/ETHERTX3
PI0/ETHERMDC
PI1/ETHERMDIO
PI2/ETHERCOL
PI3/ETHERCRS
PI4/ETHERRXER
PI5/ETHERRX0
PI6/ETHERRX1
PI7/ETHERRX2
nRESETIN
nRESETOUT
XTALIN
XTALOUT
XTAL32IN
XTAL32OUT
CLKOUT
nTRST
TMS
TCK
TDI
TDO
TEST1
TEST2
LINREGEN
VDDC
VSSC
VDD
VSS
VDDA0
VDDA1
VDDA2
VSSA0
VSSA1
VSSA2
SIGNAL NAME
ETHERCOL
MULTIPLEXED
FUNCTION(S)
Ground Core GND
Ground Input/Output GND
Ground Analog GND for Analog-to-Digital Converter
Ground Analog GND for the USB PLL
Ground Analog GND for System PLL
Power Core Power Supply
Power Input/Output Power Supply
Power Analog Power Supply for Analog-to-Digital Converter
Power Analog Power Supply for the USB PLL
Power Analog Power Supply for System PLL
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Table 5. LH79525 Pin Descriptions (Cont’d)
General Purpose I/O Signals — Port H7; multiplexed with Ethernet Transmit Channel 3
General Purpose I/O Signals — Port I0; multiplexed with Ethernet Management
Data Clock
General Purpose I/O Signals — Port I1; multiplexed with Ethernet Management Data I/O
General Purpose I/O Signals — Port I2; multiplexed with Ethernet Collision Detect
General Purpose I/O Signals — Port I3; multiplexed with Ethernet Carrier Sense
General Purpose I/O Signals — Port I4; multiplexed with Ethernet Receive Error
General Purpose I/O Signals — Port I5; multiplexed with Ethernet Receive Channel 0
General Purpose I/O Signals — Port I6; multiplexed with Ethernet Receive Channel 1
General Purpose I/O Signals — Port I7; multiplexed with Ethernet Receive Channel 2
Reset Input
Reset Output
Crystal Input, or external clock input
Crystal Output
32.768 kHz Crystal Oscillator Input, or external clock input,
32.768 kHz Crystal Oscillator Output
Clock Out (selectable from the internal bus clock or 32.768 MHz)
JTAG Test Reset Input
JTAG Test Mode Select Input
JTAG Test Clock Input
JTAG Test Serial Data Input
JTAG Test Data Serial Output
Tie HIGH for Normal Operation; pull LOW to enable embedded ICE Debugging
Tie HIGH for Normal Operation; pull HIGH to enable embedded ICE Debugging
Linear Regulator Enable (Requires pull-up. See User’s Guide)
OUTPUT
DRIVE
8 mA
NXP Semiconductors
Rev. 01 — 16 July 2007
NOTES
1
NO.
PIN
2
Table 6. LH79525 Numerical Pin List (Cont’d)
FUNCTION
AT RESET
DESCRIPTION
PI1
ETHERMDIO
MULTIPLEXED
FUNCTION(S)
Preliminary data sheet
System-on-Chip
OUTPUT
DRIVE
8 mA
NOTES
2