lh79524 NXP Semiconductors, lh79524 Datasheet - Page 26

• Manufacturer Part Number: lh79524
• Description: Lh79524; Lh79525 System-on-chip
• Manufacturer: NXP Semiconductors

LH79524/LH79525
Ethernet MAC Controller
compatible with IEEE 802.3, and has passed the Uni-
versity of New Hampshire (UNH) testing. It supports
both 10- and 100-Mbit/s, and full and half duplex oper-
ation. Other features include:
• Statistics counter registers for RMON/MIB
• MII interface to the physical layer
• Interrupt generation to signal receive and transmit
• Transmit and receive FIFOs
• Automatic pad and CRC generation on transmitted
• Automatic discard of frames received with errors
• Address checking logic supports up to four specific
• Supports promiscuous mode where all valid
• Hash matching of unicast and multicast destination
• Supports physical layer management through MDIO
• Supports serial network interface operation
• Support for:
• Multiple buffers per receive and transmit frame
• Software configures the MAC address
• Jumbo frames of up to 10,240 bytes supported.
I
interface capable of operating in either Master or Slave
mode. The block conforms to the I
cation for data rates up to 400 kbit/s. The two wires are
SCL (serial clock) and SDA (serial data). The I
ule provides the following features:
• Two-wire synchronous serial interface
• Operates in both the standard mode, for data rates
• Communicates with devices in the fast mode as well
26
2
C Controller
completion
frames
(hardware) 48-bit addresses
received frames are copied to memory
addresses
interface
up to 100 kbit/s, and the fast mode, with data rates
up to 400 kbit/s
as the standard mode if both are attached to the bus.
The on-board Ethernet MAC Controller (EMAC) is
– Half duplex flow control by forcing collisions on in-
– Full duplex flow control with recognition of incom-
– 802.Q VLAN tagging with recognition of incoming
The I
coming frames
ing pause frames and hardware generation of
transmitted pause frames
VLAN and priority tagged frames
2
C Controller includes a two-wire I
2
C 2.1 Bus Specifi-
NXP Semiconductors
Rev. 01 — 16 July 2007
2
2
C serial
C mod-
SSP To I
verts a synchronous serial communication stream in TI
DSP-compatible mode into an I
nous serial stream. The I
serial data in both master and slave mode.
• Programmable Word Select (WS) delay
• Left/right channel information:
• Ability to invert WS state
• Ability to invert the bit clock
• Supports frame size of 16 bits only. Any other frame
• Master and slave modes supported
• As with the SSP, a single combined interrupt is gen-
• Additional interrupts:
• A set of Interrupt registers contain all the information
• Additional status bits:
• Passes SSP data unaltered when module is not
• Loopback Test Mode support.
size will result in a frame size error. Each frame
transmits starting with the most-significant bit.
erated as an OR function of the individual interrupt
requests. This interrupt replaces the SSP interrupt,
which is used solely as an input to the I
in the SSPIMSC, SSPRIS, and SSPMIS registers,
plus the transmit underrun error and frame size errors
enabled
The SSP to I
The I
– Current WS value at the pin
– WS value associated with next entry written to
– WS value associated with next entry read from
– Transmit FIFO underrun
– Transmit frame size error
– Receive frame size error
– Transmit FIFO Full
– Receive FIFO Empty
TX FIFO
RX FIFO
2
S converter provides:
2
S Converter
2
S converter is an interface that con-
2
S converter operates on
Preliminary data sheet
2
S compliant synchro-
System-on-Chip
2
S converter.