lh7a400 NXP Semiconductors, lh7a400 Datasheet - Page 36
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lh7a400
Manufacturer Part Number
lh7a400
Description
Lh7a400 32-bit System-on-chip
Manufacturer
NXP Semiconductors
Datasheet
1.LH7A400.pdf
(65 pages)
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LH7A400
SMC Waveforms
timing for an External Asynchronous Memory Write.
Note that the deassertion of nWE can precede the
36
Figure 10 and Figure 11 show the waveform and
Figure 10. External Asynchronous Memory Write with 0 Wait States (BCRx:WST1 = 0b000)
A[27:0]
D[31:0]
HCLK
nCSx
nBLE
nWE
0
tAVBE
tAVWE
tAVCS
1
Rev. 01 — 16 July 2007
NXP Semiconductors
nBLE Valid
nWE Valid
VALID ADDRESS
tDVWE,
tDVBE
tBEW
tWE
VALID DATA
nCS Valid
2
tWC
tCS
deassertion of nCS by a maximum of one HCLK, or at
minimum, can coincide (see Table 12). Figure 12 and
Figure 13 show the waveform and timing for an Exter-
nal Asynchronous Memory Read.
WRITE EDGE
tDHWE,
tDHBE
tCSHWE
tCSHBE
3
tAHCS
4
32-Bit System-on-Chip
Preliminary data sheet
LH7A400-201