c8051f563 Silicon Laboratories, c8051f563 Datasheet - Page 254
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c8051f563
Manufacturer Part Number
c8051f563
Description
Mixed Signal Isp Flash Mcu Family
Manufacturer
Silicon Laboratories
Datasheet
1.C8051F563.pdf
(302 pages)
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Parameter
Master Mode Timing
T
T
T
T
Slave Mode Timing
T
T
T
T
T
T
T
T
T
T
*Note: T
MCKH
MCKL
MIS
MIH
SE
SD
SEZ
SDZ
CKH
CKL
SIS
SIH
SOH
SLH
SYSCLK
Description
SCK High Time
SCK Low Time
MISO Valid to SCK Shift Edge
SCK Shift Edge to MISO Change
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
Last SCK Edge to MISO Change
(CKPHA = 1 ONLY)
is equal to one period of the device system clock (SYSCLK).
*
*
(See Figure 24.10 and Figure 24.11)
(See Figure 24.8 and Figure 24.9)
Table 24.1. SPI Slave Timing Parameters
Rev. 1.0
Min
1 x T
1 x T
1 x T
2 x T
2 x T
5 x T
5 x T
2 x T
2 x T
6 x T
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
—
—
SYSCLK
SYSCLK
SYSCLK
SYSCLK
—
SYSCLK
0
+ 20
Max
4 x T
4 x T
4 x T
8 x T
—
—
—
—
—
—
SYSCLK
SYSCLK
—
—
—
—
SYSCLK
SYSCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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