c8051f563 Silicon Laboratories, c8051f563 Datasheet - Page 57
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c8051f563
Manufacturer Part Number
c8051f563
Description
Mixed Signal Isp Flash Mcu Family
Manufacturer
Silicon Laboratories
Datasheet
1.C8051F563.pdf
(302 pages)
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Gain Register Definition 6.3. ADC0GNA: ADC0 Additional Selectable Gain
Indirect Address = 0x08;
Note: This register is accessed indirectly; See
Reset
Name Reserved
Bit
7:1
Type
0
Bit
GAINADD
Reserved
Name
W
7
0
Must Write 0000000b.
ADC0 Additional Gain Bit.
Setting this bit add 1/64 (0.016) gain to the gain value in the ADC0GNH and
ADC0GNL registers.
Reserved
W
0
6
Reserved
W
5
0
Section 6.3.2
Reserved
Rev. 1.0
W
4
0
for details for writing this register.
Function
Reserved
W
3
0
C8051F55x/56x/57x
Reserved
W
2
0
Reserved GAINADD
W
1
0
W
0
1
57
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