c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 86
c8051t602
Manufacturer Part Number
c8051t602
Description
Mixed Signal Otp Eprom Mcu Family
Manufacturer
Silicon Laboratories
Datasheet
1.C8051T602.pdf
(168 pages)
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C8051T600/1/2/3/4/5
Table 10.2. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
86
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Leakage Current
V
V
Missing Clock Detector Timeout
Reset Time Delay
Minimum RST Low Time to
Generate a System Reset
DD
DD
Ramp Time for POR
Monitor Threshold (V
Parameter
RST
)
Delay between release of any
reset source and code execu-
rising edge to reset initiation
Time from last system clock
tion at location 0x0000
Ramp from 0 to 1.8 V
V
DD
I
RST = 0.0 V
OL
Conditions
= 1.8 to 3.6 V
= 8.5 mA,
Rev. 0.5
0.7 x V
TBD
Min
300
—
—
—
—
—
15
DD
TBD
Typ
450
25
—
—
—
—
—
—
0.3 x V
TBD
Max
600
0.6
40
60
—
1
DD
Units
ms
µA
µs
µs
µs
V
V
V
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