mc9s08qe4 Freescale Semiconductor, Inc, mc9s08qe4 Datasheet - Page 10

• Manufacturer Part Number: mc9s08qe4
• Description: 8-bit Hcs08 Central Processor Unit
• Manufacturer: Freescale Semiconductor, Inc

Electrical Characteristics
T
T
P
P
P
For most applications, P
is:
Solving
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P
for a known T
for any value of T
3.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions must be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.
10
JA
A
D
int
I/O
= Ambient temperature, qC
= P
= I
= Package thermal resistance, junction-to-ambient, qC/W
= Power dissipation on input and output pins — user determined
int
DD
Equation 1
P
u V
ESD Protection and Latch-Up Immunity
I/O
A
DD
. Using this value of K, the values of P
Latch-up
Machine
Model
Human
, Watts — chip internal power
Body
A
No.
.
1
2
and
I/O
Equation 2
P
Series resistance
Storage capacitance
Number of pulses per pin
Series resistance
Storage capacitance
Number of pulses per pin
Minimum input voltage limit
Maximum input voltage limit
Human body model (HBM)
Machine model (MM)
Table 6. ESD and Latch-Up Protection Characteristics
int
and can be neglected. An approximate relationship between P
for K gives:
Table 5. ESD and Latch-up Test Conditions
Description
K = P
Rating
D
Subject to Change Without Notice
P
u (T
1
D
MC9S08QE8 Series, Rev. 3
= K y (T
A
D
+ 273qC) + T
and T
Preliminary
J
J
+ 273qC)
can be obtained by solving
Symbol
Symbol
V
V
R1
R1
JA
HBM
—
—
—
—
C
C
MM
u (P
D
)
2
r2000
r200
Min
Value
1500
–2.5
100
200
7.5
Equation 1
3
0
3
Max
—
—
D
and T
and
Freescale Semiconductor
J
Equation 2
(if P
Unit
Unit
pF
pF
:
—
:
—
V
V
V
V
D
I/O
(at equilibrium)
is neglected)
iteratively
Eqn. 2
Eqn. 3