mc9s08ac16 Freescale Semiconductor, Inc, mc9s08ac16 Datasheet - Page 266

• Manufacturer Part Number: mc9s08ac16
• Description: Hcs08 Microcontrollers 8-bit Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 14 Analog-to-Digital Converter (S08ADC10V1)
14.5.4.2
A conversion is completed when the result of the conversion is transferred into the data result registers,
ADC1RH and ADC1RL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is
high at the time that COCO is set.
A blocking mechanism prevents a new result from overwriting previous data in ADC1RH and ADC1RL
if the previous data is in the process of being read while in 10-bit MODE (the ADC1RH register has been
read but the ADC1RL register has not). When blocking is active, the data transfer is blocked, COCO is not
set, and the new result is lost. In the case of single conversions with the compare function enabled and the
compare condition false, blocking has no effect and ADC operation is terminated. In all other cases of
operation, when a data transfer is blocked, another conversion is initiated regardless of the state of ADCO
(single or continuous conversions enabled).
If single conversions are enabled, the blocking mechanism could result in several discarded conversions
and excess power consumption. To avoid this issue, the data registers must not be read after initiating a
single conversion until the conversion completes.
14.5.4.3
Any conversion in progress will be aborted when:
When a conversion is aborted, the contents of the data registers, ADC1RH and ADC1RL, are not altered
but continue to be the values transferred after the completion of the last successful conversion. In the case
that the conversion was aborted by a reset, ADC1RH and ADC1RL return to their reset states.
14.5.4.4
The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the
conversion clock source, the ADACK clock generator is also enabled.
Power consumption when active can be reduced by setting ADLPC. This results in a lower maximum value
for f
14.5.4.5
The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus
frequency, the conversion mode (8-bit or 10-bit), and the frequency of the conversion clock (
the module becomes active, sampling of the input begins. ADLSMP is used to select between short and
long sample times.When sampling is complete, the converter is isolated from the input channel and a
successive approximation algorithm is performed to determine the digital value of the analog signal. The
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ADCK
A write to ADC1SC1 occurs (the current conversion will be aborted and a new conversion will be
initiated, if ADCH are not all 1s).
A write to ADC1SC2, ADC1CFG, ADC1CVH, or ADC1CVL occurs. This indicates a mode of
operation change has occurred and the current conversion is therefore invalid.
The MCU is reset.
The MCU enters stop mode with ADACK not enabled.
(see the electrical specifications).
Completing Conversions
Aborting Conversions
Power Control
Total Conversion Time
MC9S08AC16 Series Data Sheet, Rev. 0
PRELIMINARY
Freescale Semiconductor
f
ADCK
). After