mcimx27- Freescale Semiconductor, Inc, mcimx27- Datasheet - Page 51

• Manufacturer Part Number: mcimx27-
• Description: Multimedia Applications Processor
• Manufacturer: Freescale Semiconductor, Inc

HCLK = AHB System Clock, THCLK = Period for HCLK, Tp = Period of CSI_PIXCLK
The limitation on pixel clock rise time/fall time is not specified. It should be calculated from the hold
time and setup time based on the following assumptions:
Rising-edge latch data:
In most of case, duty cycle is 50/50, therefore:
Freescale Semiconductor
VSYNC
HSYNC
PIXCLK
DATA[7:0]
max rise time allowed = (positive duty cycle
max fall time allowed = (negative duty cycle
max rise time = (period/2
max fall time = (period/2
Number
Figure 10. CSI Timing Diagram, Gated, PIXCLK—Sensor Data at Rising Edge,
1
2
3
4
5
6
7
csi_vsync to csi_hsync
csi_hsync to csi_pixclk
csi_d setup time
csi_d hold time
csi_pixclk high time
csi_pixclk low time
csi_pixclk frequency
1
Table 21. Gated Clock Mode Timing Parameters
—
Parameter
—
Preliminary—Subject to Change Without Notice
Valid Data
setup time)
i.MX27 and i.MX27L Data Sheet, Rev. 1.2
hold time)
3
Latch Data at Falling Edge
2
4
—
—
hold time)
setup time)
Minimum
9*T
T
T
Valid Data
HCLK
HCLK
HCLK
1
1
0
3
5
7
Maximum
(Tp/2)-3
HCLK/2
6
—
—
—
—
—
Valid Data
MHz
Unit
ns
ns
ns
ns
ns
ns
Signal Descriptions
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