mcimx27- Freescale Semiconductor, Inc, mcimx27- Datasheet - Page 55

• Manufacturer Part Number: mcimx27-
• Description: Multimedia Applications Processor
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
1
2
3
4
5
The output SCLK transition time is tested with 25pF drive.
T
T
T
T
wait
Num
sclk
per
ipg
t10
t11
t12
t13
t14
t1’
t2’
t3’
t5’
t6’
t7’
ID
t1
t2
t3
t4
t5
t6
t7
t8
t9
= CSPI main clock IPG_CLOCK period
= CSPI reference baud rate clock period (PERCLK2)
= Wait time as per the Sample Period Control Register value.
= CSPI clock period
CSPI master SCLK cycle time
CSPI master SCLK high time
CSPI master SCLK low time
CSPI slave SCLK cycle time
CSPI slave SCLK high time
CSPI slave SCLK low time
CSPI SCLK transition time
SSn output pulse width
SSn input pulse width
SSn output asserted to first SCLK edge (SS output
setup time)
SSn input asserted to first SCLK edge (SS input
setup time)
CSPI master: Last SCLK edge to SSn deasserted
(SS output hold time)
CSPI slave: Last SCLK edge to SSn deasserted
(SS input hold time)
CSPI master: CSPI1_RDY low to SSn asserted
(CSPI1_RDY setup time)
CSPI master: SSn deasserted to CSPI1_RDY low
Output data setup time
Output data hold time
Input data setup time
Input data hold time
Pause between data word
Parameter Description
Table 23. CSPI Interface Timing Parameters
Preliminary—Subject to Change Without Notice
i.MX27 and i.MX27L Data Sheet, Rev. 1.2
Symbol
t
t
t
t
t
t
t
Hdatao
t
t
Sdatao
t
t
t
Hdatai
t
t
t
t
Sdatai
pause
t
t
clkoH
clkoL
Wsso
Ssso
Hsso
t
clkiH
t
Wssi
Srdy
Hrdy
clkiL
Sssi
Hssi
clko
clki
pr
1
(t
t
2T
clkoL
t
clkoL
clkiL
t
clkiL
Minimum
sclk
T
ipg
3T
2T
45.12
22.65
22.47
2T
T
or t
T
60.2
30.1
30.1
or t
or t
T
2.6
2
30
per
or t
ipg
per
0
0
0
+ 0.5
sclk
sclk
+T
per
clkoH
clkoH
clkiH
5
4
clkiH
wait
) -
or
3
or
Maximum
5T
8.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-
per
Signal Descriptions
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
—
—
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